ELECTRONIC DEVICE AND ASSOCIATED CONTROL METHOD FOR REDUCING POWER CONSUMPTION

    公开(公告)号:US20210278892A1

    公开(公告)日:2021-09-09

    申请号:US16884055

    申请日:2020-05-27

    Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.

    Method for performing power saving control in a memory device, associated memory device and memory controller thereof, and associated electronic device

    公开(公告)号:US10936046B2

    公开(公告)日:2021-03-02

    申请号:US16273166

    申请日:2019-02-12

    Abstract: A method for performing power saving control in memory device, the associated memory device and memory controller thereof, and the associated electronic device are provided, where the method is applicable to the memory controller, and the memory device includes the memory controller and a non-volatile (NV) memory. The method may include: during transmitting to a host device, sending end of burst (EOB)-related symbols to the host device, in order to notify the host device of EOB; controlling a physical layer (PHY) circuit to turn off a clock source within the PHY circuit, in order to save power, wherein the PHY circuit is positioned in a transmission interface circuit within the memory controller, and the transmission interface circuit is arranged to perform communications with the host device for the memory device; and when receiving a trigger signal from the host device, utilizing the PHY circuit to turn on the clock source.

    Memory controller and data processing method for processing disordered read-out data

    公开(公告)号:US12223173B2

    公开(公告)日:2025-02-11

    申请号:US18116801

    申请日:2023-03-02

    Abstract: A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.

    Memory controller and data processing method for processing disordered read-out data

    公开(公告)号:US20230305711A1

    公开(公告)日:2023-09-28

    申请号:US18116801

    申请日:2023-03-02

    CPC classification number: G06F3/0613 G06F3/0679 G06F3/0656

    Abstract: A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.

    METHOD AND APPARATUS FOR PERFORMING ACCESS MANAGEMENT OF MEMORY DEVICE IN PREDETERMINED COMMUNICATIONS ARCHITECTURE WITH AID OF FLEXIBLE DELAY TIME CONTROL

    公开(公告)号:US20230012997A1

    公开(公告)日:2023-01-19

    申请号:US17475366

    申请日:2021-09-15

    Abstract: A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.

    Method and apparatus for performing link management of memory device in predetermined communications architecture with aid of handshaking phase transition control

    公开(公告)号:US11972113B2

    公开(公告)日:2024-04-30

    申请号:US17874270

    申请日:2022-07-26

    CPC classification number: G06F3/0617 G06F3/0635 G06F3/0679

    Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.

    METHOD AND APPARATUS FOR PERFORMING LINK MANAGEMENT OF MEMORY DEVICE IN PREDETERMINED COMMUNICATIONS ARCHITECTURE WITH AID OF HANDSHAKING PHASE TRANSITION CONTROL

    公开(公告)号:US20240036738A1

    公开(公告)日:2024-02-01

    申请号:US17874270

    申请日:2022-07-26

    CPC classification number: G06F3/0617 G06F3/0679 G06F3/0635

    Abstract: A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.

    Method and apparatus for performing access management of memory device in predetermined communications architecture with aid of flexible delay time control

    公开(公告)号:US11636055B2

    公开(公告)日:2023-04-25

    申请号:US17475366

    申请日:2021-09-15

    Abstract: A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.

    Electronic device and associated control method for reducing power consumption

    公开(公告)号:US11112855B1

    公开(公告)日:2021-09-07

    申请号:US16884055

    申请日:2020-05-27

    Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.

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