公开(公告)号：US11901912B1

公开(公告)日：2024-02-13

申请号：US17933195

申请日：2022-09-19

Applicant: Silicon Motion, Inc.

Inventor： Shiuan-Hao Kuo ,  Zhen-U Liu

IPC: H03M13/11 ,  H03M13/15

CPC classification number: H03M13/1128 ,  H03M13/1111 ,  H03M13/1575

Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.

公开(公告)号：US10811075B1

公开(公告)日：2020-10-20

申请号：US16543639

申请日：2019-08-19

Applicant: Silicon Motion Inc.

Inventor： Chiao-Wen Cheng ,  Zhen-U Liu

IPC: G11C11/406 ,  G11C8/20 ,  G11C7/22 ,  G06F12/0802 ,  G06N20/00 ,  G11C11/409

Abstract: A method for performing access control regarding quality of service (QoS) optimization of a memory device with aid of machine learning an associated apparatus (e.g. the memory device and a controller thereof) are provided. The method may include: performing background scan on the NV memory to collect valley information of voltage distribution of memory cells within the NV memory, and performing machine learning based on a reinforcement learning model according to the valley information, in order to prepare a plurality of tables through the machine learning based on the reinforcement learning model in advance, for use of reading data from the NV memory; during a first time interval, writing first data and read the first data using a first table within the plurality of tables; and during a second time interval, reading the first data using a second table within the plurality of tables.

公开(公告)号：US09195539B2

公开(公告)日：2015-11-24

申请号：US13943755

申请日：2013-07-16

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Zhen-U Liu

IPC: G11C29/00 ,  G06F11/10 ,  G11B20/18 ,  H03M13/29 ,  H03M13/27

CPC classification number: G06F11/1068 ,  G06F11/1008 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1076 ,  G11B20/1833 ,  H03M13/27 ,  H03M13/29

Abstract: A method for reading data from a block of a flash memory is provided, where the block includes a plurality of pages and at least one parity page, each of the pages includes a plurality of sectors used for storing data and associated row parities, each of the sectors of the parity page is used to store a column parity. The method includes: reading data from a specific page of the pages; decoding the data of the specific page; and when a specific sector of the specific page fails to be decoded, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector.

Abstract translation: 提供了一种从闪速存储器块读取数据的方法，其中该块包括多个页面和至少一个奇偶校验页面，每个页面包括用于存储数据和相关行行奇偶校验的多个扇区，每个扇区 奇偶校验页面的扇区用于存储列奇偶校验。 该方法包括：从页面的特定页面读取数据; 解码特定页面的数据; 并且当特定页面的特定扇区不能被解码时，顺序地读取页面和奇偶校验页面的所有原始数据，并且根据页面的原始数据的至少一部分和特定扇区执行错误校正，并且 对应于特定扇区的奇偶校验页。

公开(公告)号：US09454430B2

公开(公告)日：2016-09-27

申请号：US14642760

申请日：2015-03-10

Applicant: Silicon Motion Inc.

Inventor： Zhen-U Liu

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/35

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  H03M13/116 ,  H03M13/35 ,  H03M13/6516

Abstract: A method for controlling a memory apparatus and the associated memory apparatus thereof and the associated controller thereof are provided, where the method includes: reading encoded data of a second set of error correction configuring parameters from a system block, and utilizing an LDPC engine to decode the encoded data to obtain the second set of error correction configuring parameters, where the LDPC engine stores a first set of error correction configuring parameters, and during decoding the encoded data, the LDPC engine performs decoding corresponding to a first LDPC characteristic matrix based on the first set of error correction configuring parameters; and controlling the LDPC engine to perform operations corresponding to a second LDPC characteristic matrix based on the second set of error correction configuring parameters in RAM, in order to make the LDPC engine be equipped with new encoding and decoding capabilities corresponding to the second LDPC characteristic matrix.

Abstract translation: 提供了一种用于控制存储装置及其相关联的存储装置及其关联控制器的方法，其中该方法包括：从系统块读取第二组纠错配置参数的编码数据，并利用LDPC引擎解码 所述编码数据以获得所述第二组纠错配置参数，其中所述LDPC引擎存储第一组纠错配置参数，并且在解码所述编码数据期间，所述LDPC引擎基于所述第一LDPC特征矩阵执行对应于第一LDPC特征矩阵的解码 第一组纠错配置参数; 以及基于所述RAM中的所述第二组纠错配置参数来控制所述LDPC引擎执行与第二LDPC特征矩阵相对应的操作，以使所述LDPC引擎配备与所述第二LDPC特征矩阵相对应的新的编码和解码能力 。