公开(公告)号：US09418744B2

公开(公告)日：2016-08-16

申请号：US14275362

申请日：2014-05-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Anh Ly ,  Victor Markov

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C8/10 ,  G11C7/02 ,  G11C16/14

CPC classification number: G11C16/14 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/3427

Abstract: An improved control gate decoding design may reduce disturbances during the programming of flash memory cells. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.

Abstract translation: 改进的控制门解码设计可以减少在闪速存储器单元的编程期间的干扰。 在一个实施例中，控制栅极线解码器耦合到与第一扇区中的一行闪存单元相关联的第一控制栅极线和耦合到与第二扇区中的一行闪存单元相关联的第二控制栅极线。

公开(公告)号：US20150325300A1

公开(公告)日：2015-11-12

申请号：US14275362

申请日：2014-05-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Anh Ly ,  Victor Markov

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/3427

Abstract: An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.

Abstract translation: 公开了一种改进的控制门解码设计，用于在闪速存储器单元的编程期间减少干扰。 在一个实施例中，控制栅极线解码器耦合到与第一扇区中的一行闪存单元相关联的第一控制栅极线和耦合到与第二扇区中的一行闪存单元相关联的第二控制栅极线。