公开(公告)号：US06524910B1

公开(公告)日：2003-02-25

申请号：US09670329

申请日：2000-09-27

申请人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

发明人： Wenhe Lin ,  Kin Leong Pey ,  Mei Sheng Zhou ,  Zhong Dong ,  Simon Chooi

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/31662 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518

摘要： A process for forming a first group of gate structures, designed to operate at a lower voltage than a simultaneously formed second group of gate structures, has been developed. The process features the thermal growth of a first silicon dioxide gate insulator layer, on a portion of the semiconductor substrate used for the lower voltage gate structures, while simultaneously forming a thicker, second silicon dioxide gate insulator layer on a portion of the semiconductor substrate used for the higher voltage gate structures. The thermal growth of the first, and second silicon dioxide gate insulator layers is accomplished via diffusion of the oxidizing species: through a thick, composite silicon nitride layer, to obtain the thinner, first silicon dioxide gate insulator layer, on a first portion of the semiconductor substrate; and through a thinner, silicon nitride layer, to obtain the thicker, second silicon dioxide gate insulator layer, on a second portion of the semiconductor substrate.

摘要翻译： 已经开发了一种用于形成第一组栅极结构的工艺，其设计成在比同时形成的第二组栅极结构低的电压下工作。 该方法的特征在于在用于低电压栅极结构的半导体衬底的一部分上的第一二氧化硅栅极绝缘体层的热生长，同时在所使用的半导体衬底的一部分上形成较厚的第二二氧化硅栅极绝缘体层 对于较高电压门结构。 第一和第二二氧化硅栅极绝缘体层的热生长通过氧化物质的扩散来实现：通过厚的复合氮化硅层，以获得较薄的第一二氧化硅栅极绝缘体层，在第一部分 半导体衬底; 并通过较薄的氮化硅层，以在半导体衬底的第二部分上获得较厚的第二二氧化硅栅极绝缘体层。

公开(公告)号：US07005716B2

公开(公告)日：2006-02-28

申请号：US10853454

申请日：2004-05-25

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

公开(公告)号：US06750519B2

公开(公告)日：2004-06-15

申请号：US10266714

申请日：2002-10-08

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2976

CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。 此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06677652B2

公开(公告)日：2004-01-13

申请号：US10227697

申请日：2002-08-26

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

公开(公告)号：US06458695B1

公开(公告)日：2002-10-01

申请号：US09981416

申请日：2001-10-18

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2144

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将氧离子注入到一个活性区域中的金属层中，以形成被氧化形成金属氧化物层的注入金属层。 此后，金属层和金属氧化物层被图案化以在一个有源区域中形成金属栅极，而在另一个有源区域中形成金属氧化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属氧化物栅极，其中两个栅极的氧化物浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是氧注入和氧化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06835989B2

公开(公告)日：2004-12-28

申请号：US10736943

申请日：2003-12-16

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将氧离子注入到一个活性区域中的金属层中，以形成被氧化形成金属氧化物层的注入金属层。 此后，金属层和金属氧化物层被图案化以在一个有源区域中形成金属栅极，而在另一个有源区域中形成金属氧化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属氧化物栅极，其中两个栅极的氧化物浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是氧注入和氧化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06486080B2

公开(公告)日：2002-11-26

申请号：US09726656

申请日：2000-11-30

申请人： Simon Chooi ,  Wenhe Lin ,  Mei Sheng Zhou

发明人： Simon Chooi ,  Wenhe Lin ,  Mei Sheng Zhou

IPC分类号： H01L2131

CPC分类号： H01L21/02271 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/31604 ,  H01L21/31691

摘要： A new method of forming a metal oxide high dielectric constant layer in the manufacture of an integrated circuit device has been achieved. A substrate is provided. A metal oxide layer is deposited overlying the substrate by reacting a precursor with an oxidant gas in a chemical vapor deposition chamber. The metal oxide layer may comprise hafnium oxide or zirconium oxide. The precursor may comprise metal alkoxide, metal alkoxide containing halogen, metal &bgr;-diketonate, metal fluorinated &bgr;-diketonate, metal oxoacid, metal acetate, or metal alkene. The metal oxide layer is annealed to cause densification and to complete the formation of the metal oxide dielectric layer in the manufacture of the integrated circuit device. A composite metal oxide-silicon oxide (MO2-SiO2) high dielectric constant layer may be deposited using a precursor comprising metal tetrasiloxane.

摘要翻译： 已经实现了在制造集成电路器件中形成金属氧化物高介电常数层的新方法。 提供基板。 通过在化学气相沉积室中使前体与氧化剂气体反应而沉积在衬底上的金属氧化物层。 金属氧化物层可以包括氧化铪或氧化锆。 前体可以包含金属醇盐，含有卤素的金属醇盐，β-二酮金属，氟化β-二酮金属，金属氧代酸，金属乙酸盐或金属烯烃。 在集成电路器件的制造中，对金属氧化物层进行退火以致致密化并完成金属氧化物介电层的形成。 可以使用包含金属四硅氧烷的前体来沉积复合金属氧化物 - 氧化硅（MO2-SiO2）高介电常数层。

公开(公告)号：US06475908B1

公开(公告)日：2002-11-05

申请号：US09981415

申请日：2001-10-18

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L2144

CPC分类号： H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。 此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06891233B2

公开(公告)日：2005-05-10

申请号：US10736942

申请日：2003-12-16

申请人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

发明人： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823842

摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

摘要翻译： 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将氧离子注入到一个活性区域中的金属层中，以形成被氧化形成金属氧化物层的注入金属层。 此后，金属层和金属氧化物层被图案化以在一个有源区域中形成金属栅极，而在另一个有源区域中形成金属氧化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属氧化物栅极，其中两个栅极的氧化物浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是氧注入和氧化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06534388B1

公开(公告)日：2003-03-18

申请号：US09670330

申请日：2000-09-27

申请人： Wenhe Lin ,  Zhong Dong ,  Simon Chooi ,  Kin Leong Pey

发明人： Wenhe Lin ,  Zhong Dong ,  Simon Chooi ,  Kin Leong Pey

IPC分类号： H01L2104

CPC分类号： H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

摘要： A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD region and overlying silicon oxide regions, retarding the diffusion of boron from the LDD regions to the overlying silicon oxide regions, during subsequent high temperature anneals. The nitrogen containing layer, such as a thin silicon nitride layer, or a silicon oxynitride layer, formed during or after reoxidation of a P type polysilicon gate structure, is also formed in a region that also retards the out diffusion of P type dopants from the P type polysilicon gate structure.

摘要翻译： 已经开发了用于阻止P型掺杂剂从P型LDD区扩散的过程，导致不希望的LDD串联电阻增加。 该过程的特征在于形成含氮层，放置在P型LDD区域和覆盖的氧化硅区域之间，在随后的高温退火期间阻止硼从LDD区域扩散到覆盖的氧化硅区域。 在P型多晶硅栅极结构再氧化期间或之后形成的氮化硅层或氮氧化硅层等氮含量层也形成在也延缓P型掺杂剂从 P型多晶硅栅结构。