公开(公告)号：US20120221834A1

公开(公告)日：2012-08-30

申请号：US13219321

申请日：2011-08-26

申请人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty ,  Fabienne Hegarty

发明人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty ,  Fabienne Hegarty

IPC分类号： G06F15/76 ,  G06F9/06 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30163 ,  G06F9/30185 ,  G06F9/345 ,  G06F9/3889

摘要： A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

摘要翻译： 一种处理器，包括：第一和至少第二数据处理通道，其具有用于选择性地启用第二通道的使能逻辑; 用于基于相同存储访问指令的相同一个或多个地址操作数产生具有可变偏移的第一和第二存储地址的逻辑; 以及用于基于访问指令的相同的一个或多个寄存器指定器操作数，在第一数据处理通道的第一地址和寄存器之间以及第二地址和第二通道的相应寄存器之间传送数据的电路。 第一数据处理通道使用第一数据处理通道的一个或多个寄存器来执行操作，并且在使能的条件下，第二通道使用相应的一个或多个基于相同的一个或多个寄存器的相应操作 数据处理指令的操作数。

公开(公告)号：US08782376B2

公开(公告)日：2014-07-15

申请号：US13219321

申请日：2011-08-26

申请人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty

发明人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC分类号： G06F9/30043 ,  G06F9/30163 ,  G06F9/30185 ,  G06F9/345 ,  G06F9/3889

摘要： A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

摘要翻译： 一种处理器，包括：第一和至少第二数据处理通道，其具有用于选择性地启用第二通道的使能逻辑; 用于基于相同存储访问指令的相同一个或多个地址操作数产生具有可变偏移的第一和第二存储地址的逻辑; 以及用于基于访问指令的相同的一个或多个寄存器指定器操作数，在第一数据处理通道的第一地址和寄存器之间以及第二地址和第二通道的相应寄存器之间传送数据的电路。 第一数据处理通道使用第一数据处理通道的一个或多个寄存器来执行操作，并且在使能的条件下，第二通道使用相应的一个或多个基于相同的一个或多个寄存器的相应操作 数据处理指令的操作数。

公开(公告)号：US20120192028A1

公开(公告)日：2012-07-26

申请号：US13393022

申请日：2010-08-26

申请人： Steve Allpress ,  Colman Hegarty ,  Carlo Luschi ,  Fabienne Hegarty

发明人： Steve Allpress ,  Colman Hegarty ,  Carlo Luschi ,  Fabienne Hegarty

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H04L1/005 ,  G06F11/10 ,  H03M13/05 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3905 ,  H03M13/3972 ,  H03M13/6362 ,  H03M13/653 ,  H04L1/0055 ,  H04L1/0066 ,  H04L1/0068

摘要： A method, apparatus and program. The method comprises: receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states; for each symbol in the sequence, determining a set of state metrics each representing a probability that the respective symbol corresponds to each of the plurality of states; and decoding the signal by processing runs of recursions, using runs of forward recursions and runs of reverse recursions. The decoding comprises performing a plurality of repeated iterations over the sequence, and for each iteration: dividing the sequence into a plurality of smaller windows, processing the windows using separate runs of recursions, and performing an associated warm-up run of recursions for each window. The decoding further comprises, for each repeated recursion: alternating the direction of the warm-up runs between forward and reverse with each successive iteration over the sequence, storing one of the sets of state metrics from each window, and initialising the warm-up run of each window using a corresponding stored set of state metrics from a previous iteration.

摘要翻译： 方法，装置和程序。 该方法包括：接收包括编码符号序列的信号，每个对应于多个可能状态之一; 对于序列中的每个符号，确定一组状态度量，每个状态度量表示各个符号对应于多个状态中的每一个的概率; 并通过处理递归运算来解码信号，使用正向递归运行和反向递归运行。 解码包括在序列上执行多次重复迭代，并且对于每次迭代，将该序列划分成多个较小的窗口，使用单独的递归运算来处理窗口，并且对每个窗口执行相关的预热运行递归运算 。 对于每个重复的递归，解码还包括：在序列之间的每个连续迭代中交替在正向和反向之间的预热运行的方向，存储来自每个窗口的状态度量集合中的一个，并且初始化预热运行 使用来自先前迭代的相应的存储的状态度量集合。

公开(公告)号：US20110191507A1

公开(公告)日：2011-08-04

申请号：US13057679

申请日：2009-05-26

申请人： Andrew Bond ,  Peter Cumming ,  Colman Hegarty ,  Fabienne Hegarty

发明人： Andrew Bond ,  Peter Cumming ,  Colman Hegarty ,  Fabienne Hegarty

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors.

摘要翻译： 一种电路，包括：执行单元; 多个可寻址装置; 以及耦合到所述执行单元和所述设备的数据传输引擎，用于在所述执行单元的控制下获取多个描述符，并且基于每个所述获取的描述符，以执行数据从相应的第一到第 第二个设备。 DMA引擎包括延迟电路，其可操作以在延迟时段期间从更早的传输中阻止任何稍后的传输，其涉及与早期传输相同的设备中的至少一个，延迟电路被布置为控制阻塞 依赖于在其中一个描述符中接收到的指示。

公开(公告)号：US08509367B2

公开(公告)日：2013-08-13

申请号：US12330905

申请日：2008-12-09

申请人： Stephen Felix ,  Colman Hegarty

发明人： Stephen Felix ,  Colman Hegarty

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

摘要翻译： 本发明提供一种接收机，包括数据输入和选通输入。 当数据信号中的两个连续位相同时，选通信号转换。 接收机包括用于从数据和选通信号的组合产生恢复的时钟信号的组合装置。 接收机还包括第一采样级，其被布置为根据恢复的时钟信号对数据信号进行采样，第一采样级包括多个采样电路，并且被布置为使用交替的采样电路来获得数据信号的连续采样 。 第二采样级被设置为根据本地系统时钟信号对来自第一采样级的数据进行采样。

公开(公告)号：US20090147888A1

公开(公告)日：2009-06-11

申请号：US12330905

申请日：2008-12-09

申请人： Stephen Felix ,  Colman Hegarty

发明人： Stephen Felix ,  Colman Hegarty

IPC分类号： H04L7/00 ,  H04L7/04 ,  H04L27/06

CPC分类号： H04L7/0008

摘要： The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

摘要翻译： 本发明提供一种接收机，包括数据输入和选通输入。 当数据信号中的两个连续位相同时，选通信号转换。 接收机包括用于从数据和选通信号的组合产生恢复的时钟信号的组合装置。 接收机还包括第一采样级，其被布置为根据恢复的时钟信号对数据信号进行采样，第一采样级包括多个采样电路，并且被布置为使用交替的采样电路来获得数据信号的连续采样 。 第二采样级被设置为根据本地系统时钟信号对来自第一采样级的数据进行采样。

公开(公告)号：US08793561B2

公开(公告)日：2014-07-29

申请号：US13393022

申请日：2010-08-26

申请人： Steve Allpress ,  Carlo Luschi ,  Fabienne Hegarty

发明人： Steve Allpress ,  Colman Hegarty ,  Carlo Luschi

IPC分类号： H03M13/00 ,  H04L1/00 ,  H03M13/05 ,  H03M13/29 ,  H03M13/37 ,  H03M13/39 ,  G06F11/10

CPC分类号： H04L1/005 ,  G06F11/10 ,  H03M13/05 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3905 ,  H03M13/3972 ,  H03M13/6362 ,  H03M13/653 ,  H04L1/0055 ,  H04L1/0066 ,  H04L1/0068

摘要： One aspect provides a method. The method comprises receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states. For each symbol in the sequence, the method further comprises determining a set of state metrics, each representing a probability that the respective symbol corresponds to the plurality of states. The method further comprises decoding the signal by processing runs of recursions using runs of forward recursions, whereby a later state metric in the sequence is updated based on a preceding state metric, and runs of recursions using runs of reverse recursions, whereby a preceding state metric in the sequence is updated based on a later state metric. The method further comprises outputting the decoded signal to a device. The decoding comprises performing a plurality of repeated iterations over the sequence.

摘要翻译： 一方面提供了一种方法。 该方法包括接收包括编码符号序列的信号，每一个对应于多个可能状态之一。 对于序列中的每个符号，该方法还包括确定一组状态度量，每一个表示各个符号对应于多个状态的概率。 该方法还包括使用正向递归运算来处理递归运算来对信号进行解码，由此基于先前状态度量来更新序列中的后续状态度量，并且使用反向递归运算来运行递归，由此前一状态度量 在该序列中基于稍后的状态度量来更新该序列。 该方法还包括将解码的信号输出到设备。 解码包括在序列上执行多次重复迭代。

公开(公告)号：US07996581B2

公开(公告)日：2011-08-09

申请号：US12466038

申请日：2009-05-14

申请人： Andrew Bond ,  Peter Cumming ,  Colman Hegarty

发明人： Andrew Bond ,  Peter Cumming ,  Colman Hegarty

IPC分类号： G06F13/28

CPC分类号： G06F13/30

摘要： A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.

摘要翻译： 一种用于传输数据的电路和相应的方法。 该电路包括：CPU; 多个可寻址装置; 以及耦合到CPU和那些设备的DMA引擎，DMA引擎包括多个DMA上下文，每个DMA上下文具有用于取出由CPU指示的DMA描述符的读取电路和用于基于 一个获取的描述符。 DMA引擎还包括切换装置，其可操作以控制一组上下文在获取和执行传送之间的互补序列中交替，使得当一个或多个其他执行传送时，组提取中的一个或多个上下文交替。

公开(公告)号：US20090287859A1

公开(公告)日：2009-11-19

申请号：US12466038

申请日：2009-05-14

申请人： Andrew Bond ,  Peter Cumming ,  Colman Hegarty

发明人： Andrew Bond ,  Peter Cumming ,  Colman Hegarty

IPC分类号： G06F13/28

CPC分类号： G06F13/30

摘要： A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.

摘要翻译： 一种用于传输数据的电路和相应的方法。 该电路包括：CPU; 多个可寻址装置; 以及耦合到CPU和那些设备的DMA引擎，DMA引擎包括多个DMA上下文，每个DMA上下文具有用于取出由CPU指示的DMA描述符的读取电路和用于基于 一个获取的描述符。 DMA引擎还包括切换装置，其可操作以控制一组上下文在获取和执行转移之间的互补序列中交替，使得在一个或多个其他执行转移时组中取代中的一个或多个上下文交替。