公开(公告)号：US08352764B2

公开(公告)日：2013-01-08

申请号：US12286188

申请日：2008-09-29

申请人： Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

发明人： Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/3209 ,  Y02D10/171 ,  Y02D50/20

摘要： In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括用于静噪检测电路的功率控制逻辑，以使得能够以低功率模式选择性地启用互连接口的一个或多个静噪检测电路。 逻辑可以包括静噪模式控制寄存器以选择第一模式或第二模式的功率控制;第二寄存器，耦合到静噪模式控制寄存器以接收软件设置，以指示哪个静噪检测电路在低电平中禁用 互连的功率状态，以及用于在第二模式中动态地检测互连的逻辑通道零点的检测器。 描述和要求保护其他实施例。

公开(公告)号：US20100081406A1

公开(公告)日：2010-04-01

申请号：US12286188

申请日：2008-09-29

申请人： Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

发明人： Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

IPC分类号： H04B1/10

CPC分类号： G06F1/3287 ,  G06F1/3209 ,  Y02D10/171 ,  Y02D50/20

摘要： In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括用于静噪检测电路的功率控制逻辑，以使得能够以低功率模式选择性地启用互连接口的一个或多个静噪检测电路。 逻辑可以包括静噪模式控制寄存器以选择第一模式或第二模式的功率控制;第二寄存器，耦合到静噪模式控制寄存器以接收软件设置，以指示哪个静噪检测电路在低电平中禁用 互连的功率状态，以及用于在第二模式中动态地检测互连的逻辑通道零点的检测器。 描述和要求保护其他实施例。

公开(公告)号：US20080235461A1

公开(公告)日：2008-09-25

申请号：US11726563

申请日：2007-03-22

申请人： Sin Tan ,  Kai Cheng ,  Rajesh S. Pamujula ,  Sivakumar Radhakrishnan ,  Dhananjay Joshi

发明人： Sin Tan ,  Kai Cheng ,  Rajesh S. Pamujula ,  Sivakumar Radhakrishnan ,  Dhananjay Joshi

IPC分类号： G06F13/28

CPC分类号： G06F13/1663 ,  G06F13/1668

摘要： A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available.

摘要翻译： 一个桥包括一个建立事务表和写入组合窗口的内存。 每个写入组合窗口与高速缓存行相关联，并被细分为子窗口; 并且每个子窗口与部分高速缓存行相关联。 该桥包括一个控制器，用于确定传入的部分写入事务是否与存储在事务表中的事务冲突。 如果发生冲突，则如果部分写入组合窗口之一可用，则控制器使用写入组合窗口将部分写入事务与另一个部分写入事务组合。 如果没有部分写入组合窗口可用，则控制器向发起部分写入事务的处理器发出重试信号。

公开(公告)号：US20060168384A1

公开(公告)日：2006-07-27

申请号：US10977230

申请日：2004-10-29

申请人： Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  Sin Tan ,  Suneeta Sah

发明人： Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  Sin Tan ,  Suneeta Sah

IPC分类号： G06F13/24

CPC分类号： G06F13/385

摘要： Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.

公开(公告)号：US20080040899A1

公开(公告)日：2008-02-21

申请号：US11572412

申请日：2005-07-08

申请人： Sin Tan

发明人： Sin Tan

IPC分类号： A44B21/00 ,  A44B13/00 ,  A44C5/00

CPC分类号： A44C5/2019 ,  Y10T24/3427 ,  Y10T24/3484 ,  Y10T24/3493 ,  Y10T24/44239 ,  Y10T24/44291 ,  Y10T24/45016

摘要： The present invention relates generally to a versatile clip for jewellery which functions as the link between the necklace and exchangeable pieces of jewellery comprising a front member (4) and a rear member (6) having curved profiles and hinged at one end whilst the respective engaging ends (10A), (10B) of the front and rear members (4), (6) opposing the hinge (8) are capable of being integrally latched to assume a central aperture (12); said engaging end (10A) of the front member (4) opposing the hinge (8) is provided with an indented notch (16A) to accommodate a hook (18) having one end (20) permanently fixed on the outer surface (22) of the front member (4) adjacent to the base (16C) of the indented notch (16A) and one unfixed end (24) freely extending into the indented notch (16A); said engaging end (10B) of the rear member (6) opposing the hinge (8) is also provided with an indented notch (16B) to snugly encompass the free unfixed end (24) of the hook (18) to hold the pendant captive when the engaging ends (10A) (10B) are latched in interlocking relationship.

摘要翻译： 本发明总体上涉及一种用于首饰的通用夹子，其用作项链和可更换的首饰之间的连接件，其包括前部构件（4）和具有弯曲轮廓的后部构件（6），并且在相应的接合处 与铰链（8）相对的前部和后部构件（4），（6）的端部（10A），（10B）能够被一体地锁定以呈现中心孔（12）; 前部构件（4）的与铰链（8）相对的所述接合端部（10A）设置有凹口（16A）以容纳具有永久固定在外表面上的一端（20）的钩（18） （16A）相邻的前部构件（4）的一个未固定端（24）和一个自由延伸到凹口（16A）中的未固定端部; 后部构件（6）的与铰链（8）相对的所述接合端部（10B）还设置有凹口（16B），以紧密地包围钩子（18）的自由未固定端部（24）以保持 当接合端（10A）（10B）以互锁关系锁定时，吊坠圈闭。

公开(公告)号：US20050060502A1

公开(公告)日：2005-03-17

申请号：US10970015

申请日：2004-10-21

申请人： Sin Tan ,  Stanley Kulick ,  Rajesh Pamujula

发明人： Sin Tan ,  Stanley Kulick ,  Rajesh Pamujula

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0835

摘要： A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.

摘要翻译： 转发设备将来自第一相干输入/输出（I / O）事务的第一地址与来自至少一个处理器发出的事务的地址进行比较，以确定是否存在地址冲突。 如果地址冲突存在并且拒绝第一个相干I / O事务，则转发设备完成所述至少一个处理器发布的交易的第一处理器发出的交易。 所述转发设备保持所述至少一个处理器发布的交易的剩余处理器事务，其具有与所述第一相干I / O事务的第一地址冲突的地址。 转发设备将第一个相干I / O事务发送到外部I / O设备，等待第一个相干I / O事务从外部I / O设备返回，并完成第一个相干I / O事务。 一旦完成了第一个相干I / O事务，转发设备将释放剩余的处理器事务。

公开(公告)号：US6134632A

公开(公告)日：2000-10-17

申请号：US013094

申请日：1998-01-26

申请人： Lily Pao Looi ,  Sin Tan ,  John Urbanski ,  Christopher Van Beek

发明人： Lily Pao Looi ,  Sin Tan ,  John Urbanski ,  Christopher Van Beek

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0835 ,  G06F12/0804 ,  Y10S707/99942

摘要： A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line. Also provided is a method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory-write operation. The method includes setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to slices of a word line associated with the set slice enable bits in the slice-addressable random access memory buffer; and write-merging data from the modified cache line to slices of the word line not associated with the set slice-enable bits in the slice-addressable random access memory buffer.

摘要翻译： 公开了一种包括片可寻址多端口存储器阵列的计算机系统。 片可寻址的多端口存储器阵列提供了一种用于根据关联的片启用位阵列在存储器控制器中有效地数据合并的机制。 存储器阵列的每个片段由片启用位分别指定，并且在写操作期间仅修改由片启用位指定的能够写入的字线的那些片。 在随后的写合并操作中，修改了在写操作期间未被片使能位指定的写入字线的片，并且在前一写操作期间被修改的片不受影响，从而提供 来自写入操作的数据的高效合并和来自写入合并操作的数据在单个字线中。 还提供了当在存储器写入操作期间检测到高速缓存中的修改的行上的命中时，在计算机系统中保持高速缓存一致性的方法。 该方法包括设置与通过存储器写入操作修改的高速缓存行的每个片段相关联的限幅使能位; 将数据写入与所述片可寻址随机存取存储器缓冲器中的所述设置片使能位相关联的字线的片; 以及从所述修改的高速缓存行将所述数据写入到与所述片可寻址随机存取存储器缓冲器中的所述设置的片使能位不相关联的字线的片。

公开(公告)号：US5996038A

公开(公告)日：1999-11-30

申请号：US13773

申请日：1998-01-26

申请人： Lily Pao Looi ,  Sin Tan ,  James Andrew Sutton, II

发明人： Lily Pao Looi ,  Sin Tan ,  James Andrew Sutton, II

IPC分类号： G06F13/40 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4045

摘要： A computer system including individually resettable bus expander bridges is described. A master bus controller provides an interface between at least one processor and at least one independently resettable bus expander bridge associated with one or more expansion buses. A bus expander bridge can be reset independently from the rest of the system when the master bus controller asserts a reset control signal that is applied to the bus expander bridge without affecting the operation of any other bus expander bridges or devices in the computer system not directly coupled to the expansion bus(es) being reset. When a reset control signal is asserted, the bus expander bridge being reset and the bus(es) associated with the bus expander bridge are reset to a default state. Once the reset process has had sufficient time for completion, the reset control signal is deasserted by the master bus controller and the bus expander bridge resumes operation.

摘要翻译： 描述了包括单独可复位的总线扩展器桥的计算机系统。 主总线控制器提供至少一个处理器与至少一个与一个或多个扩展总线相关联的可独立复位的总线扩展器桥接口。 当主总线控制器断言施加到总线扩展器桥的复位控制信号，而不直接影响计算机系统中任何其他总线扩展器桥或器件的操作时，总线扩展器桥可以独立于系统的其余部分复位 耦合到扩展总线被复位。 当复位控制信号被断言时，总线扩展器桥被复位，并且与总线扩展器桥相关联的总线被复位到默认状态。 一旦复位过程已经有足够的时间完成，复位控制信号被主总线控制器断开，总线扩展器桥恢复运行。