公开(公告)号：US20200335474A1

公开(公告)日：2020-10-22

申请号：US16916136

申请日：2020-06-30

Applicant: Sitronix Technology Corp.

Inventor： Ying-Chen Chang ,  Po-Chi Chen ,  Kuo-Wei Tseng

IPC: H01L23/00

Abstract: A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.

公开(公告)号：US20180114769A1

公开(公告)日：2018-04-26

申请号：US15792767

申请日：2017-10-25

Applicant: Sitronix Technology Corp.

Inventor： Ying-Chen Chang ,  Po-Chi Chen ,  Kuo-Wei Tseng

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13144 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16502 ,  H01L2224/73253 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2924/00014

Abstract: A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.