公开(公告)号：US11978776B2

公开(公告)日：2024-05-07

申请号：US16461071

申请日：2016-12-12

申请人： Intel Corporation

发明人： Ashutosh Sagar ,  Sridhar Govindaraju

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/456 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/16502 ,  H01L2924/01322 ,  H01L2924/014

摘要： An apparatus includes a non-planar semiconductor body; and a contact for the semiconductor body. The contact includes an epitaxial material that is formed on and contacts the semiconductor body. The contact includes a second material that is formed on and contacts the epitaxial material; and the second material at least partially conforms to an undercut of the epitaxial material.

公开(公告)号：US09136237B2

公开(公告)日：2015-09-15

申请号：US14109616

申请日：2013-12-17

申请人： Oracle International Corporation

发明人： Hiren D. Thacker ,  John E. Cunningham

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/16502 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/00012

摘要： This chip package includes a substrate having a multilayer electroplated stack disposed on a surface of the substrate. The multilayer electroplated stack may include one or more instances of alternating layers of gold and tin, where relative thicknesses of the alternating layers, when melted, result in a chemical composition having an initial melting temperature to form a bump and a subsequent melting temperature to reflow the bump that is higher than the initial melting temperature. For example, the chemical composition may correspond to a non-equilibrium gold-tin alloy.

摘要翻译： 该芯片封装包括具有设置在基板的表面上的多层电镀堆叠的基板。 多层电镀堆叠可以包括金和锡的交替层的一个或多个实例，其中交替层的相对厚度在熔化时导致化学组成具有初始熔融温度以形成凸块和随后的熔融温度以回流 该凸起高于初始熔化温度。 例如，化学组成可以对应于非平衡金 - 锡合金。

公开(公告)号：US11676926B2

公开(公告)日：2023-06-13

申请号：US17000966

申请日：2020-08-24

申请人： Schlumberger Technology Corporation

发明人： Mark Alex Kostinovsky ,  Steven O. Dunford ,  Lweness Mazari

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L2224/03019 ,  H01L2224/03464 ,  H01L2224/05147 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/08502 ,  H01L2224/11019 ,  H01L2224/11464 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/16502 ,  H01L2224/4312 ,  H01L2224/43125 ,  H01L2224/45147 ,  H01L2224/45655 ,  H01L2224/48225 ,  H01L2224/48506 ,  H01L2224/80355 ,  H01L2224/81355 ,  H01L2224/85355 ,  H01L2924/15747

摘要： A method for interconnecting two conductors includes creating a first nickel layer on a first conductor of an electrical component, producing a first non-gold protective layer on the first nickel layer, the first non-gold protective layer being configured to prevent the first nickel layer from oxidizing, creating a second nickel layer on a second conductor, producing a second non-gold protective layer on the second nickel layer, the second non-gold protective layer being configured to prevent the second nickel layer from oxidizing, and interconnecting the first and second nickel layers using a solder layer that interfaces with the first and second nickel layers between the first and second conductors.

公开(公告)号：US20180114769A1

公开(公告)日：2018-04-26

申请号：US15792767

申请日：2017-10-25

申请人： Sitronix Technology Corp.

发明人： Ying-Chen Chang ,  Po-Chi Chen ,  Kuo-Wei Tseng

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13144 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16502 ,  H01L2224/73253 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2924/00014

摘要： A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead, wherein the gold bump includes a first bonding surface and a plurality of side walls. The gold bump is electrically connected to the inner lead through a eutectic material coverage layer, and the first bonding surface and at least one of the plurality of side walls are covered by the eutectic material coverage layer.

公开(公告)号：US20160204313A1

公开(公告)日：2016-07-14

申请号：US15078734

申请日：2016-03-23

申请人： DEXERIALS CORPORATION

发明人： Hidetsugu NAMIKI ,  Shiyuki KANISAWA ,  Akira ISHIGAMI

IPC分类号： H01L33/38 ,  H01L33/48 ,  H01B1/22 ,  H01L33/62

CPC分类号： H01L33/62 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/1184 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13644 ,  H01L2224/16238 ,  H01L2224/16502 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81395 ,  H01L2224/81444 ,  H01L2224/81805 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83395 ,  H01L2224/83444 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/83885 ,  H01L2224/9221 ,  H01L2933/0016 ,  H01L2933/0066 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2224/83801

摘要： In order to provide a light emitting device having high connection reliability, the light-emitting device includes a board provided with a wiring pattern, an anisotropic conductive paste arranged on an board electrode of the wiring pattern, and a light-emitting element embedded in the anisotropic conductive paste, and at least one of the board electrode and the element electrode is plated with an AuSn alloy layer. The anisotropic conductive paste contains an epoxy compound, an acid anhydride, white inorganic particles, and conductive particles obtained by coating resin particles with an Au coating layer. It is possible to maintain electrical connection between the board electrode and the element electrode by the Au coating layers of the conductive particles even when a crack is generated in a eutectic bonding portion. Therefore, it is possible to obtain high connection reliability.

摘要翻译： 为了提供具有高连接可靠性的发光装置，发光装置包括设置有布线图案的基板，布置在布线图案的基板电极上的各向异性导电浆料和嵌入在该布线图案中的发光元件 各向异性导电膏，并且板电极和元件电极中的至少一个电镀有AuSn合金层。 各向异性导电糊包含环氧化合物，酸酐，白色无机颗粒和通过用Au涂层涂覆树脂颗粒而获得的导电颗粒。 即使在共晶接合部中产生裂纹，也可以通过导电性粒子的Au被覆层来保持基板电极与元件电极之间的电连接。 因此，可以获得高连接可靠性。

公开(公告)号：US09136232B2

公开(公告)日：2015-09-15

申请号：US14344274

申请日：2012-09-27

申请人： OMRON Corporation

发明人： Takeshi Fujiwara ,  Toshiaki Okuno ,  Katsuyuki Inoue ,  Junya Yamamoto ,  Kenichi Hinuma ,  Yoshiki Ashihara ,  Takaaki Miyaji

IPC分类号： H01L23/00 ,  H01L23/02 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/10 ,  H01L21/50 ,  B81C1/00

CPC分类号： H01L24/05 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/50 ,  H01L23/02 ,  H01L23/10 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/06182 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/14181 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16502 ,  H01L2224/16506 ,  H01L2224/2908 ,  H01L2224/29171 ,  H01L2224/3201 ,  H01L2224/32058 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/83193 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for bonding wafers includes forming a first bonding part on a surface of a first wafer by stacking a diffusion preventing layer formed of a material having low wettability with AuSn above the first wafer and forming a bonding layer on a surface of the diffusion preventing layer such that the bonding layer stays back of an edge of the diffusion preventing layer, forming a second bonding part on a surface of a second wafer, and bonding the first bonding part and the second bonding part by eutectic bonding with an AuSn solder under a condition that the first wafer and the second wafer are opposed to each other.

摘要翻译： 一种用于接合晶片的方法包括：在第一晶片的上方堆叠由具有低吸湿性的材料形成的扩散防止层，在第一晶片的表面上形成第一接合部分，并在扩散防止层的表面上形成接合层 使得接合层停留在扩散防止层的边缘的后面，在第二晶片的表面上形成第二接合部分，并且在条件下通过与AuSn焊料的共晶接合来接合第一接合部分和第二接合部分 第一晶片和第二晶片彼此相对。

公开(公告)号：US11805685B2

公开(公告)日：2023-10-31

申请号：US17205419

申请日：2021-03-18

申请人： Samsung Display Co., Ltd.

发明人： Youngmin Cho ,  Hongam Kim

IPC分类号： H10K59/131 ,  H01L23/00

CPC分类号： H10K59/131 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/06132 ,  H01L2224/06135 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16502 ,  H01L2224/29198 ,  H01L2224/32145 ,  H01L2224/73204

摘要： The present application relates to an electronic device. The electronic device includes a first electronic component and a second electronic component. The first electronic component includes a first pad area including first pads and second pads spaced apart from the first pads. A number of the first pads is greater than a number of the second pads. The second electronic component includes first bumps electrically connected to the first pads, and second bumps electrically connected to the second pads. Each of the second bumps has a bonding area greater than a bonding area of each of the first bumps. A conductive adhesive layer is disposed between the first electronic component and the second electronic component to electrically connect the first pads to the first bumps.

公开(公告)号：US20180286836A1

公开(公告)日：2018-10-04

申请号：US15921563

申请日：2018-03-14

申请人： Silicon Storage Technology, Inc.

发明人： Justin Hiroki Sato ,  Bomy Chen ,  Walter Lundy

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0217 ,  H01L2224/0219 ,  H01L2224/04042 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/16502 ,  H01L2224/48091 ,  H01L2224/81143 ,  H01L2224/81805 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/07025 ,  H01L2224/45099

摘要： A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

公开(公告)号：US20170066088A1

公开(公告)日：2017-03-09

申请号：US14846489

申请日：2015-09-04

申请人： Intel Corporation

发明人： Mohit Sood ,  Boxi Liu ,  Wei Tan ,  Huili Xu ,  Kabir J. Mirpuri

IPC分类号： B23K35/26 ,  B23K35/02 ,  H01L23/00 ,  H05K3/36 ,  H01L21/48 ,  H05K1/18 ,  H05K1/14 ,  H05K3/34 ,  B23K1/00 ,  H01L23/498

CPC分类号： B23K35/262 ,  B23K1/0016 ,  B23K35/0244 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/1339 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16502 ,  H01L2224/16505 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8192 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/363 ,  H05K2201/042 ,  H05K2201/10234 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/041 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01323 ,  H01L2924/01324 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/0665

摘要： Embodiments herein may relate to an apparatus with a ball grid array (BGA) package that includes a plurality of solder balls of an off-eutectic material. In embodiments, the respective solder balls of the plurality of solder balls may form solder joints between a substrate of the BGA and a second substrate. In some embodiments the joints may be less than approximately 0.6 micrometers from one another. Other embodiments may be described and/or claimed.

摘要翻译： 本文的实施例可以涉及具有球栅阵列（BGA）封装的装置，其包括多个非共晶材料的焊球。 在实施例中，多个焊球的相应焊球可以在BGA的衬底和第二衬底之间形成焊接接头。 在一些实施例中，接头可以彼此小于约0.6微米。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20130087906A1

公开(公告)日：2013-04-11

申请号：US13253088

申请日：2011-10-05

申请人： Pai-Sheng Cheng ,  Chia-Hui Wu

发明人： Pai-Sheng Cheng ,  Chia-Hui Wu

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13624 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16058 ,  H01L2224/16502 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/8185 ,  H01L2224/83193 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention provides a circuit board including a substrate, at least one lead, at least one bump, and a solder layer. The lead is disposed on the substrate, and the bump is disposed on the lead. The solder layer covers the lead and the bump.

摘要翻译： 本发明提供一种电路板，其包括基板，至少一个引线，至少一个凸块和焊料层。 引线设置在基板上，并且凸块设置在引线上。 焊料层覆盖引线和凸块。