公开(公告)号：US12107062B2

公开(公告)日：2024-10-01

申请号：US17694995

申请日：2022-03-15

申请人： Texas Instruments Incorporated

发明人： Rafael Jose Guevara

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L23/49822 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/05691 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/11849 ,  H01L2224/13019 ,  H01L2224/13024 ,  H01L2224/13553 ,  H01L2224/13575 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2924/381 ,  H01L2924/3841

摘要： A semiconductor die includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads that include a first die bond pad exposed by a passivation layer, a top dielectric layer over the passivation layer, and a metal layer electrically connected to the first die bond pad. A pillar is on the metal layer over the first die bond pad, and a solder cap is on a top side of the pillar. The solder cap includes an essentially vertical sidewall portion generally beginning at a top corner edge of the pillar.

公开(公告)号：US20240038704A1

公开(公告)日：2024-02-01

申请号：US17874206

申请日：2022-07-26

申请人： Micron Technology, Inc.

发明人： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2924/37001 ,  H01L2924/3512 ,  H01L2224/16148 ,  H01L2224/16221 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/1355 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/13582

摘要： In some embodiments, a semiconductor device assembly can include a first semiconductor die, a second semiconductor die, and an interconnection structure therebetween. The interconnection structure can directly electrically couple the first and the second semiconductor dies. The interconnection structure can include an inner metallic pillar, an outer metallic shell, a continuous metallic bridging layer, and a dielectric liner. The outer metallic shell can surround and be spaced from the inner metallic pillar, the continuous metallic bridging layer can be over and connected with the inner metallic pillar and the outer metallic shell, and the dielectric liner can be between the inner metallic pillar and the outer metallic shell. In some embodiments, the second semiconductor die can be excluded and the interconnection structure can solely be coupled to the first semiconductor die.

公开(公告)号：US20230260958A1

公开(公告)日：2023-08-17

申请号：US18306832

申请日：2023-04-25

申请人： Texas Instruments Incorporated

发明人： Rafael Jose Lizares Guevara ,  John Carlo Cruz Molina ,  Steffany Ann Lacierda Moreno

IPC分类号： H01L23/00 ,  H01L21/48

CPC分类号： H01L24/81 ,  H01L21/4828 ,  H01L24/96 ,  H01L24/97 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13144 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2924/17747 ,  H01L2224/13019 ,  H01L2224/16258 ,  H01L2224/13147 ,  H01L2224/81192

摘要： In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.

公开(公告)号：US20190164921A1

公开(公告)日：2019-05-30

申请号：US16263318

申请日：2019-01-31

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Charles L. Arvin ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/03 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11001 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01027

摘要： A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. A conductive via terminates at a top surface of the first conductive layer.

公开(公告)号：US20190006324A1

公开(公告)日：2019-01-03

申请号：US16125171

申请日：2018-09-07

申请人： TOSHIBA MEMORY CORPORATION

发明人： Tatsuo MIGITA ,  Koji OGISO

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/1703 ,  H01L2224/17106 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01082

摘要： A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.

公开(公告)号：US20180348259A1

公开(公告)日：2018-12-06

申请号：US16040621

申请日：2018-07-20

申请人： International Business Machines Corporation

发明人： Bing Dang ,  John Knickerbocker ,  Yang Liu ,  Maurice Mason ,  Lubomyr T. Romankiw

IPC分类号： G01R1/073 ,  H01L23/00 ,  B81C1/00 ,  G01R31/26 ,  B81B3/00 ,  B23K35/00

CPC分类号： G01R1/0735 ,  B23K35/00 ,  B81B3/00 ,  B81B2201/02 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81C1/00626 ,  G01R31/2607 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13663 ,  H01L2224/73207 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01104

摘要： A method of forming surface protrusions on an article, and the article with the protrusions attached. The article may be an Integrated Circuit (IC) chip, a test probe for the IC chip or any suitable substrate or nanostructure. The surface protrusions are electroplated to a template or mold wafer, transferred to the article and easily separated from the template wafer. Thus, the attached protrusions may be, e.g., micro-bumps or micro pillars on an IC chip or substrate, test probes on a probe head, or one or more cantilevered membranes in a micro-machine or micro-sensor or other micro-electro-mechanical systems (MEMS) formed without undercutting the MEMS structure.

公开(公告)号：US10056347B2

公开(公告)日：2018-08-21

申请号：US15413058

申请日：2017-01-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Wei Chiu ,  Tzu-Yu Wang ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Hsien-Wei Chen ,  Hung-An Teng ,  Wei-Cheng Wu

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  B23K1/00 ,  C23C18/32 ,  C23C18/42 ,  C23C14/16 ,  C23C14/34

CPC分类号： H01L24/81 ,  B23K1/0016 ,  C23C14/165 ,  C23C14/34 ,  C23C18/32 ,  C23C18/42 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/10125 ,  H01L2224/114 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/8112 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00

摘要： A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

公开(公告)号：US20180068931A1

公开(公告)日：2018-03-08

申请号：US15685640

申请日：2017-08-24

申请人： Samsung Display Co., Ltd.

发明人： Seung Hwa HA ,  Jung Yun JO ,  Byoung Yong KIM ,  Jeong Do YANG ,  Jeong Ho HWANG

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/4952 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13019

摘要： A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base substrate and having an opening exposing a portion of the conductive pad; and a bump on the exposed portion of the conductive pad and on the insulating layer around the opening. The bump includes a plurality of concave portions corresponding to the opening and is arranged in a longitudinal direction of the bump.

公开(公告)号：US20180047709A1

公开(公告)日：2018-02-15

申请号：US15793325

申请日：2017-10-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/038 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05693 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48693 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48793 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48893 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01006

摘要： Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

公开(公告)号：US20180040592A1

公开(公告)日：2018-02-08

申请号：US15788094

申请日：2017-10-19

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC分类号： H01L25/065 ,  H01L25/075 ,  H01L23/40 ,  H01L23/00 ,  H01L25/04 ,  H01L23/498 ,  H01L23/34 ,  H01L25/00 ,  H01L23/367 ,  H01L23/42

CPC分类号： H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.