公开(公告)号：US20240395709A1

公开(公告)日：2024-11-28

申请号：US18796017

申请日：2024-08-06

Applicant: Socionext Inc.

Inventor： Yasumitsu SAKAI

IPC: H01L23/528 ,  G11C5/06 ,  G11C17/12 ,  H10B20/00

Abstract: A semiconductor memory device includes: a word line extending in the X direction; a bit line extending in the Y direction, formed in a buried interconnect layer; and a ground power line extending in the Y direction. A memory cell includes a transistor provided between the bit line and the ground power line, and connected to the word line at its gate and to the bit line at its drain. The memory cell stores data depending on the presence or absence of connection between the source of the transistor and the ground power line.

公开(公告)号：US20250151268A1

公开(公告)日：2025-05-08

申请号：US19013630

申请日：2025-01-08

Applicant: Socionext Inc.

Inventor： Yasumitsu SAKAI

IPC: H10B20/00 ,  H10D30/43 ,  H10D30/67 ,  H10D62/10

Abstract: A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.

公开(公告)号：US20240112746A1

公开(公告)日：2024-04-04

申请号：US18538722

申请日：2023-12-13

Applicant: SOCIONEXT INC.

Inventor： Yasumitsu SAKAI ,  Shinichi MORIWAKI

IPC: G11C17/12 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C17/12 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

公开(公告)号：US20250151267A1

公开(公告)日：2025-05-08

申请号：US19015181

申请日：2025-01-09

Applicant: Socionext Inc.

Inventor： Yasumitsu SAKAI

IPC: H10B20/00

Abstract: A ROM cell using a complementary FET (CFET) includes: a first three-dimensional transistor provided between a first bit line and a first ground power supply line, and a second three-dimensional transistor provided between a second bit line and a second ground power supply line. Channel portions of the first and second transistors overlap each other in planar view. First data is stored depending on the presence or absence of connection between the source of the first transistor and the first ground power supply line. Second data is stored depending on the presence or absence of connection between the source of the second transistor and the second ground power supply line. The first and second bit lines are formed in a buried interconnect layer.

公开(公告)号：US20220310634A1

公开(公告)日：2022-09-29

申请号：US17842473

申请日：2022-06-16

Applicant: Socionext Inc.

Inventor： Yasumitsu SAKAI

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

公开(公告)号：US20220130478A1

公开(公告)日：2022-04-28

申请号：US17524535

申请日：2021-11-11

Applicant: SOCIONEXT INC.

Inventor： Yasumitsu SAKAI ,  Shinichi MORIWAKI

IPC: G11C17/12 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/06

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

公开(公告)号：US20220068942A1

公开(公告)日：2022-03-03

申请号：US17524369

申请日：2021-11-11

Applicant: Socionext Inc.

Inventor： Yasumitsu SAKAI

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.