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1.发明申请Heterogeneous parallel multithread processor (HPMT) with shared contexts 有权具有共享上下文的异构并行多线程处理器（HPMT）公开(公告)号：US20050193186A1
公开(公告)日：2005-09-01
申请号：US11064795
申请日：2005-02-24
申请人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
发明人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
CPC分类号： G06F9/3851 , G06F9/3012 , G06F9/30123 , G06F9/3802 , G06F9/3891
摘要： The invention relates to a heterogeneous parallel multithread processor (1) with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (2p; pε[1, . . . , M]), where each respective standard processor root unit type (2p) has at least one or more (K) parallel-connected standard processor root units (2pq; qε[1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type (2p) having N local context memories (32pt) which each buffer-store part of a current processor state for a thread. The multithread processor (1) also has a plurality (N) of global context memories (3t; tε[1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit (4) which can connect any standard processor root unit (2pq) to any global context memory (3t).
摘要翻译： 本发明涉及具有共享上下文的异构并行多线程处理器（1），所述共享上下文具有多个（M）并行连接的标准处理器根单元类型（2＆lt; p＆gt;; pepsilon [1，...， M]），其中每个相应的标准处理器根单元类型（2P）具有至少一个或多个（K）并联连接的标准处理器根单元（2＆lt; pq＆gt; 用于从各种线程（T）指令执行程序指令的qepsilon [1，...，K]），具有N个本地上下文存储器的每个标准处理器根单元类型（2 > pt ），其中每个缓冲区存储线程当前处理器状态的一部分。 多线程处理器（1）还具有多个（N）个全局上下文存储器（3），每个缓冲器存储当前处理器状态的一部分 以及线程控制单元（4），其可以将任何标准处理器根单元（2 >）与任何全局上下文存储器（3T）进行连接。
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公开(公告)号：US4841463A
公开(公告)日：1989-06-20
申请号：US75024
申请日：1987-07-15
申请人： Soenke Mehrgardt , Bernhard Ehret
发明人： Soenke Mehrgardt , Bernhard Ehret
IPC分类号： H03H17/06
CPC分类号： H03H17/06 , H03H17/0607
摘要： The signal path of a nonrecursive digital filter contains a series combination of like delay elements each providing a delay equal to the period of a clock signal or to a multiple thereof, each of the delay elements having a subtracter and a read-only memory associated therewith. The minuend inputs of each of the subtracters associated with the first half of delay elements is connected to the input of the associated delay element, and that of each of the substracters associated with the second half of delay elements to the output of the associated delay element, while the subtrahend inputs of all subtracters are connected to the center tap of the series combination of delay elements and to the first input of an adder. The output of each of the subtracters is coupled to the address input of the associated read-only memory, which has its output connected to one of the inputs of a multiple-input adder. The output of the latter is fed to the second input of the adder. Each read-only memory contains the function e=bd, where d is the output signal of the subtracter, and b is a value dependent on the difference between the center-tap signal value and the input-signal value of the respective delay element of the first half of delay elements or the output-signal value of the respective delay element of the second half. This digital filter shows adaptive behavior.
摘要翻译： 非递归数字滤波器的信号路径包含类似延迟元件的串联组合，每个延迟元件提供等于时钟信号或其倍数的周期的延迟，每个延迟元件具有减法器和与其相关联的只读存储器 。 与延迟元件的前半部分相关联的每个减法器的减法输入连接到相关联的延迟元件的输入端，并且将与延迟元件的后半部分相关联的每个子字符的输入连接到相关延迟元件的输出 而所有减法器的减数输入连接到延迟元件的串联组合的中心抽头和加法器的第一输入端。 每个减法器的输出耦合到相关联的只读存储器的地址输入端，该存储器的输出端连接到多输入加法器的输入之一。 后者的输出被馈送到加法器的第二输入端。 每个只读存储器包含函数e = bd，其中d是减法器的输出信号，b是取决于中心抽头信号值与相应延迟元件的输入信号值之间的差值 延迟元件的前半部分或后半部分相应延迟元件的输出信号值。 该数字滤波器显示自适应行为。
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公开(公告)号：US4721905A
公开(公告)日：1988-01-26
申请号：US940592
申请日：1986-12-11
申请人： Soenke Mehrgardt
发明人： Soenke Mehrgardt
CPC分类号： G01R25/08
摘要： To determine the phase difference between the edge of a pulse of a first clock signal and the edge of a pulse of a second clock signal with an integrable phase meter circuit, the second clock signal is fed through a frequency-divider circuit to the input of an unclocked delay line including m delay elements, and to a second register containing m cells, while the m cells of a first register are clocked by the first clock signal. The outputs of the kth register cells are compared in the kth XOR gate of a row of m XOR gates, so that, when the levels of these outputs are unlike, a logic 1 appears at the output of the kth gate. The phase is obtained at the n-bit output of a multiple adder adding the logic levels, the accuracy corresponding to m, which is preferably equal to 2.sup.n.
摘要翻译： 为了通过可积分相位计电路确定第一时钟信号的脉冲的边缘与第二时钟信号的脉冲的边缘之间的相位差，第二时钟信号通过分频器电路馈送到 包括m个延迟元件的非锁定延迟线，以及包含m个单元的第二寄存器，而第一寄存器的m个单元由第一时钟信号计时。 在第m个异或门的第k个异或门中比较第k个寄存器单元的输出，使得当这些输出的电平不同时，逻辑1出现在第k个门的输出处。 在多加法器的n比特输出处获得该相位，其加上逻辑电平，对应于m的精度，其优选地等于2n。
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公开(公告)号：US4663595A
公开(公告)日：1987-05-05
申请号：US830976
申请日：1986-02-18
申请人： Soenke Mehrgardt , Bernhard Ehret
发明人： Soenke Mehrgardt , Bernhard Ehret
CPC分类号： H03D3/00 , H04N11/186
摘要： A subcircuit for the demodulation of SECAM color-television signals has two signal paths each including a low-pass filter (tp1, tp2) which has the transfer function H(z)=(1+ z.sup.-1).sup.5. The amount of area required by the subcircuit on an integrated-circuit chip is thus kept small.
摘要翻译： 用于解调SECAM彩色电视信号的分支电路具有两个信号路径，每个信号路径包括具有传递函数H（z）=（1 + z-1）5的低通滤波器（tp1，tp2）。 因此，集成电路芯片上的子电路所需的面积的量保持较小。
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公开(公告)号：US07526636B2
公开(公告)日：2009-04-28
申请号：US10987935
申请日：2004-11-12
申请人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
发明人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
IPC分类号： G06F9/00
CPC分类号： G06F9/3851
摘要： The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).
摘要翻译： 本发明涉及具有分离上下文的并行多线程处理器（1），其中M并行连接的标准处理器根单元（2）被提供用于指令执行不同线程（T）的程序指令，并且具有N个上下文存储器（3） ），其每个临时存储线程（T）的当前状态，并且提供线程监视单元（4），通过该线程监视单元（4）可以将每个标准处理器根单元（2）连接到每个上下文存储器 3）。 因此，本发明提供了一种处理器架构，其中不同上下文存储器（3）和相应线程（T）的数量N与数量M的标准处理器根单元（2）有效地完全联网。 这意味着不仅使用标准处理器根单元（2）并行线程（T）和上下文存储器（3）。
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公开(公告)号：US20050198476A1
公开(公告)日：2005-09-08
申请号：US10987935
申请日：2004-11-12
申请人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
发明人： Lajos Gazsi , Jinan Lin , Soenke Mehrgardt , Xiaoning Nie
CPC分类号： G06F9/3851
摘要： The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).
摘要翻译： 本发明涉及具有分离上下文的并行多线程处理器（1），其中M并行连接的标准处理器根单元（2）被提供用于指令执行针对不同线程（T）的程序指令，并且具有N个上下文存储器 ），其每个临时存储线程（T）的当前状态，并且提供线程监视单元（4），通过该线程监视单元（4）可以将每个标准处理器根单元（2）连接到每个上下文存储器 3）。 因此，本发明提供了一种处理器架构，其中不同上下文存储器（3）和相应线程（T）的数量N与数量M的标准处理器根单元（2）有效地完全联网。 这意味着使用不仅与标准处理器根单元（2）并行，而且还用于线程（T）和上下文存储器（3）的并行。
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7.发明授权Offset-compensated hall sensor having plural hall detectors having different geometrical orientations and having switchable directions 失效偏移补偿霍尔传感器具有具有不同几何取向并且具有切换方向的多个霍尔检测器
公开(公告)号：US5406202A
公开(公告)日：1995-04-11
申请号：US987918
申请日：1992-12-08
申请人： Soenke Mehrgardt , Lothar Blossfeld
发明人： Soenke Mehrgardt , Lothar Blossfeld
摘要： For improved offset compensation, a Hall sensor is provided with a device for orthogonally switching the Hall detector supply current and the Hall-voltage taps. A summing device determines an offset-compensated Hall-voltage value from first and second predetermined Hall-voltage values. The Hall-voltage values are formed by means of a Hall detector containing at least first and second Hall cells for offset-voltage precompensation. The first and second Hall cells are identical and are orthogonally switchable. The geometrical orientation of the first and second Hall cells includes an angle other than 0.degree. and 180.degree..
摘要翻译： 为了改进偏移补偿，霍尔传感器具有用于正交切换霍尔检测器电源电流和霍尔电压抽头的装置。 求和装置根据第一和第二预定霍尔电压值确定偏移补偿霍尔电压值。 通过霍尔检测器形成霍尔电压值，霍尔检测器至少包含用于偏置电压预补偿的第一和第二霍尔单元。 第一和第二霍尔单元是相同的并且是可正交切换的。 第一和第二霍尔单元的几何取向包括0°和180°以外的角度。
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8.发明授权
公开(公告)号：US5150201A
公开(公告)日：1992-09-22
申请号：US677063
申请日：1991-03-29
CPC分类号： H04N9/64
摘要： A digital television-signal-processing circuit for a composite color signal is sampled with a first clock signal. The digitized composite color signal is reconverted with a line-locked second clock signal. The two clock signals have the same frequency. A second phase-locked loop for controlling the phase of the horizontal pulse includes a locked oscillator and is loosely coupled to a first phase-locked loop which generates a horizontal reference clock. The decoupling of the data, which is referred to the two clock signals, takes place in a dual-port read/write memory which is written into synchronously with the first clock signal and read from synchronously with the second clock signal.
摘要翻译： 用第一时钟信号对合成彩色信号的数字电视信号处理电路进行采样。 数字化复合颜色信号用线锁定第二时钟信号重新转换。 两个时钟信号具有相同的频率。 用于控制水平脉冲的相位的第二锁相环包括锁定振荡器，并松耦合到产生水平参考时钟的第一锁相环。 参考两个时钟信号的数据的去耦发生在与第一时钟信号同步写入并与第二时钟信号同步读取的双端口读/写存储器中。
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9.发明授权Television receiver for flicker-free reproduction of an interlaced video signal 失效电视接收机，用于无闪烁地再现隔行扫描的视频信号
公开(公告)号：US4683497A
公开(公告)日：1987-07-28
申请号：US794518
申请日：1985-11-04
申请人： Soenke Mehrgardt
发明人： Soenke Mehrgardt
CPC分类号： H04N7/0132 , Y10S348/91
摘要： A high definition TV receiver includes a single frame memory arranged with three memory areas, three multiplexers, a movement detector, a half image interpolator and a control circuit to provide flicker-free video reproduction.
摘要翻译： 高分辨率电视接收机包括配置有三个存储区域的单帧存储器，三个多路复用器，运动检测器，半图像内插器和控制电路，以提供无闪烁的视频再现。
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公开(公告)号：US4803407A
公开(公告)日：1989-02-07
申请号：US74203
申请日：1987-07-16
申请人： Soenke Mehrgardt
发明人： Soenke Mehrgardt
CPC分类号： H04N3/2335
摘要： Instead of fine-controlling the horizontal deflection signal in a digital television receiver by means of two phase-locked loops and gate-delay stages as is done in prior art arrangements, in the horizontal-deflection circuit according to the invention, a first digital word delivered by a first phase-locked loop and representative of the horizontal frequency is added in an adder to a suitably amplified third digital word delivered by a phase comparator of a second phase-locked loop. The output of the adder is fed to the control input of a digital sine-wave generator which drives a frequency divider. The latter delivers the horizontal deflection signal, which drives the horizontal output stage. The phase comparator is fed with the horizontal flyback signal, which is derived from the horizontal deflection signal, and a second digital word generated by the first phase-locked loop and representative of the desired phase position of the flyback signal.
摘要翻译： 代替如现有技术的布置中那样通过两个锁相环和门延迟阶段精细地控制数字电视接收机中的水平偏转信号，在根据本发明的水平偏转电路中，第一数字字 通过由第二锁相环的相位比较器传送的适当放大的第三数字字，加法器将由第一锁相环递送并代表水平频率的信号相加。 加法器的输出被馈送到驱动分频器的数字正弦波发生器的控制输入端。 后者提供水平偏转信号，驱动水平输出级。 相位比较器馈送水平反激信号，其由水平偏转信号导出，第二数字字由第一锁相环产生并代表回扫信号的期望相位位置。
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