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公开(公告)号：US20170254841A1
公开(公告)日：2017-09-07
申请号：US15059151
申请日：2016-03-02
Applicant: QUALCOMM Incorporated
Inventor： Saeed Nejatali , Linda Irish , David Fern , Francesco Carobolante, II
IPC: G01R25/08
Abstract: Methods and circuitry are disclosed to produce a first signal representative of the AC voltage signal and a second signal representative of an AC current signal. The first and second signals may be combined with a clock signal to produce a third signal. A phase angle between the AC voltage signal and the AC current signal may be determined based on a pulse count indicative of how many pulses occur in the third signal over a predetermined period of time.
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公开(公告)号：US20090267666A1
公开(公告)日：2009-10-29
申请号：US12432426
申请日：2009-04-29
Applicant: Masazumi MARUTANI
Inventor： Masazumi MARUTANI
CPC classification number: G01R25/08 , H03D13/001 , H03K5/26
Abstract: A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase difference between the input clocks; and a counter unit which samples a level of the phase difference signal using a reference clock having a second frequency which is slower than the first frequency, and counts the number of levels of the phase difference signal using a first weighting according to the sampled level of the phase difference signal. When the count value of the counter unit transits in a predetermined range, the phase difference between the input clocks is detected according to the first weighting.
Abstract translation: 一种相位差检测器，用于检测具有相同第一频率的输入时钟之间的相位差，包括：脉冲宽度转换单元，用于将输入时钟转换为指示脉冲宽度的输入时钟之间的相位差的相位差信号; 以及计数器单元，其使用具有比第一频率慢的第二频率的参考时钟对相位差信号的电平进行采样，并且使用根据采样电平的采样电平的第一加权来对相位差信号的电平数进行计数 相位差信号。 当计数器单元的计数值在预定范围内转变时，根据第一加权来检测输入时钟之间的相位差。
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公开(公告)号：US20060069522A1
公开(公告)日：2006-03-30
申请号：US10970580
申请日：2004-10-20
Applicant: David Bruno
Inventor： David Bruno
IPC: G06F19/00
CPC classification number: G01R25/08 , G01R21/133
Abstract: An electricity metering method and apparatus is provided for determining the phase of first waveform relative to a harmonically distorted, second waveform having cycles temporally distinguished by an occurrence of an amplitude that is neither zero amplitude nor a maximum amplitude of said waveform.
Abstract translation: 提供一种用于确定相对于谐波失真的第二波形的第一波形的相位的电力计量方法和装置，该第二波形具有时间上由不是零幅度的振幅的出现而不是所述波形的最大幅度的区别。
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公开(公告)号：US5528200A
公开(公告)日：1996-06-18
申请号：US392246
申请日：1995-02-22
Applicant: Shigenori Yamauchi , Takamoto Watanabe , Yoshinori Ohtsuka
Inventor： Shigenori Yamauchi , Takamoto Watanabe , Yoshinori Ohtsuka
CPC classification number: H03K3/0315 , G01R25/08 , H03K5/131 , Y10S331/03
Abstract: A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal. A control signal inputting arrangement serves to input the second control signal to the second start inverting circuit during an interval from a first moment at which the first control signal is input into the first start inverting circuit and the first start inverting circuit starts the inverting operation to a second moment at which a pulse edge initially generated by the start of the inverting operation of the first start inverting circuit and travelling while being sequentially inverted by the inverting circuits enters the second start inverting circuit.
Abstract translation: 用于循环两种类型的脉冲边缘的环形振荡器包括以环形连接的偶数反相电路。 每个反相电路用于反转输入信号并输出输入信号的反相。 反相电路中的一个是第一启动反相电路，其响应于从外部输入施加的第一控制信号开始反相输入信号的操作。 除了第一启动反相电路和紧接在第一启动反相电路之后的反相电路之一的反相电路中的一个是响应于第二控制信号开始反相输入信号的操作的第二启动反相电路。 控制信号输入装置用于在从第一控制信号输入到第一启动反相电路的第一时刻起的间隔期间将第二控制信号输入到第二启动反相电路，并且第一启动反相电路开始反相操作 第二时刻，由第一起动反转电路的反相操作开始初始产生的脉冲沿并且由反相电路顺序反转的第二时刻进入第二启动反相电路。
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公开(公告)号：US5438254A
公开(公告)日：1995-08-01
申请号：US282180
申请日：1994-07-29
Applicant: Edmond Y. Ho , Fu-chin Yang , Jung-lung Lin
Inventor： Edmond Y. Ho , Fu-chin Yang , Jung-lung Lin
Abstract: A phase difference measuring device includes a phase detector, a low-pass filter/voltage controlled oscillator, a reference signal selector for selecting either an internal reference signal or an external reference signal as a reference signal, a phase comparator for comparing an undertest signal with the selected reference signal and obtaining a phase difference between the two compared signal. The internal reference signal is selected when the undertest signal is a jittering signal, and the external reference signal is selected when the undertest signal is a wandering signal. The undertest signal, the selected reference signal, and a relatively high frequency clock signal from external are sent to the phase comparator and a phase difference between the undertest signal and the selected reference signal is counted by the relatively high frequency clock signal.
Abstract translation: 相位差测量装置包括相位检测器，低通滤波器/压控振荡器，用于选择内部参考信号或外部参考信号作为参考信号的参考信号选择器，将相关信号与 所选择的参考信号并获得两个比较信号之间的相位差。 当承载信号为抖动信号时，选择内部参考信号，当承载信号为漫游信号时，选择外部参考信号。 承受信号，所选择的参考信号和来自外部的相对高频时钟信号被发送到相位比较器，并且通过相对高频时钟信号对该信号和所选参考信号之间的相位差进行计数。
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Patent Agency Ranking
公开(公告)号：US4772852A
公开(公告)日：1988-09-20
申请号：US927579
申请日：1986-11-06
Applicant: Maurizio Viti
Inventor： Maurizio Viti
Abstract: An instantaneous comparison unit with an associated sequential state logic circuit is described which functions to maintain a condition of phase locking with a reference signal which is substantially immune to disturbances which cause losses or additions of signal fronts. Continuous phase shifting conditions during the transient, which precedes phase locking, is detected and compensated for by the disclosed circuit.
Abstract translation: 描述了具有相关联的顺序状态逻辑电路的瞬时比较单元，其功能是使用基本上免于引起信号前沿的损耗或增加的干扰的参考信号来维持相位锁定的状态。 由公开的电路检测和补偿在相位锁定之前的瞬态期间的连续相移条件。
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公开(公告)号：US4721905A
公开(公告)日：1988-01-26
申请号：US940592
申请日：1986-12-11
Applicant: Soenke Mehrgardt
Inventor： Soenke Mehrgardt
CPC classification number: G01R25/08
Abstract: To determine the phase difference between the edge of a pulse of a first clock signal and the edge of a pulse of a second clock signal with an integrable phase meter circuit, the second clock signal is fed through a frequency-divider circuit to the input of an unclocked delay line including m delay elements, and to a second register containing m cells, while the m cells of a first register are clocked by the first clock signal. The outputs of the kth register cells are compared in the kth XOR gate of a row of m XOR gates, so that, when the levels of these outputs are unlike, a logic 1 appears at the output of the kth gate. The phase is obtained at the n-bit output of a multiple adder adding the logic levels, the accuracy corresponding to m, which is preferably equal to 2.sup.n.
Abstract translation: 为了通过可积分相位计电路确定第一时钟信号的脉冲的边缘与第二时钟信号的脉冲的边缘之间的相位差，第二时钟信号通过分频器电路馈送到 包括m个延迟元件的非锁定延迟线，以及包含m个单元的第二寄存器，而第一寄存器的m个单元由第一时钟信号计时。 在第m个异或门的第k个异或门中比较第k个寄存器单元的输出，使得当这些输出的电平不同时，逻辑1出现在第k个门的输出处。 在多加法器的n比特输出处获得该相位，其加上逻辑电平，对应于m的精度，其优选地等于2n。
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公开(公告)号：US4543600A
公开(公告)日：1985-09-24
申请号：US533819
申请日：1983-09-19
Applicant: Thomas V. Bolger
Inventor： Thomas V. Bolger
CPC classification number: G01R25/08
Abstract: A phase measuring arrangement for sampled signals changes the phase of the sampling signal in fine phase increments while comparing the magnitudes of the signal samples so produced to determine whether they have magnitudes within a given range of values. The range of values is indicative of a known phase angle. The number of magnitudes falling within the given range is indicative of the phase of the sampled signal relative to the known phase angle. Embodiments are disclosed in which such phase measuring arrangement is employed in a phase-locked loop useful for processing chrominance signals in a television receiver.
Abstract translation: 用于采样信号的相位测量装置以精细相位增量改变采样信号的相位，同时比较如此产生的信号样本的幅度，以确定它们是否具有在给定值范围内的幅度。 值的范围表示已知的相位角。 落在给定范围内的幅度数量表示采样信号相对于已知相位角的相位。 公开了一种实施例，其中在用于处理电视接收机中的色度信号的有用的锁相环中使用这种相位测量装置。
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公开(公告)号：US4250454A
公开(公告)日：1981-02-10
申请号：US23823
申请日：1979-03-26
Applicant: Norman Y. Sakamoto
Inventor： Norman Y. Sakamoto
CPC classification number: H03L7/0812 , G01R25/08 , G01S7/282
Abstract: An electronic trigger circuit for an RF source, which electronic trigger may be advantageously used in a radar apparatus, for instance. The trigger employs digital logic devices including a register or counter, a circuit for initiating counting in the register in response to a received pretrigger signal and a circuit responsive to the occurrence of selected count in the register for enabling the RF source. A timing signal is generated, based upon the pretrigger signal in timed relationship to the time at which the RF source should nominally generate its RF signal. Typically, the RF source generates its RF signal at sometime after being enabled. A comparator circuit is provided for comparing the phase relationship of the aforementioned timing signal and the occurrence of the RF signal and is in turn coupled to an arithmetic circuit effective for altering the number of states through which the register counts. Preferably, the arithmetic circuit alters the number of states only when the comparison circuit indicates that the phase relationship differs by some preselected period of time. Thus, each time the RF source is fired, its output is compared with the time at which the output should nominally occur and when this difference exceeds a predetermined amount, the amount of delay between the time the pretrigger signal is received and the time the RF source is enabled is varied by changing the number of states through which the aforementioned register counts.
Abstract translation: 例如，用于RF源的电子触发电路，该电子触发器可以有利地用于雷达装置中。 触发器采用包括寄存器或计数器的数字逻辑器件，用于响应于接收到的预触发信号而在寄存器中启动计数的电路和响应于寄存器中选择的计数的发生的电路以使能RF源。 基于与RF信号源名义上产生其RF信号的时间的定时关系的预触发信号，产生定时信号。 通常，RF源在启用后的某个时间产生其RF信号。 提供比较器电路，用于比较上述定时信号的相位关系和RF信号的出现，并且又连接到有效地改变寄存器计数的状态数量的运算电路。 优选地，只有当比较电路指示相位关系不同预定时间段时，算术电路才改变状态数。 因此，每当RF源被点亮时，其输出与输出应该名义上出现的时间进行比较，并且当该差异超过预定量时，接收到预触发信号的时间与RF之间的时间 源使能是通过改变上述寄存器计数的状态数来改变的。
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公开(公告)号：US4178631A
公开(公告)日：1979-12-11
申请号：US877259
申请日：1978-02-13
Applicant: Robert L. Nelson, Jr.
Inventor： Robert L. Nelson, Jr.
Abstract: A digital phase detector includes a hard limiter which transforms an incoming signal of known frequency into a binary signal at the same frequency. A reference generator produces two binary references at the signal frequency, one reference shifted 90.degree. in phase with respect to the other. The binary signal is exclusive-ORed with each reference and the exclusive-OR outputs therefrom control two counters, the counters thereby registering counts analogous to trigonometric functions of the signal phase angle. A phase modulated clock drives the counters, the phase modulation feature permitting a correction factor to be incorporated in order to cancel the error introduced by the quantized nature of the digital computations involved.
Abstract translation: 数字相位检测器包括硬限幅器，其将已知频率的输入信号以相同频率变换成二进制信号。 参考发生器在信号频率处产生两个二进制参考，一个参考相对于另一个相位移位90°。 二进制信号与每个参考值进行异或运算，其异或输出控制两个计数器，计数器由此记录类似于信号相位角的三角函数的计数。 相位调制时钟驱动计数器，相位调制特征允许并入校正因子，以便消除由所涉及的数字计算的量化特性引入的误差。
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