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公开(公告)号：US6040727A
公开(公告)日：2000-03-21
申请号：US61814
申请日：1998-04-16
申请人： Sonke Struck , Ernst Holger
发明人： Sonke Struck , Ernst Holger
摘要： A delay device includes storage elements arranged in at least two rows 4, 5; 6, 7 in an integrated circuit, preferably in switched-capacitor technology. The delay device 2; 3 has an even number of storage elements. A first clock signal is provided from which, for producing a delay time equal to an odd multiple of the clock period of the first clock signal, a second clock signal is derived by means of a clock generation circuit 9, this second clock signal clocking the storage elements and being derived from the first clock signal in such a manner that one clock pulse of the first clock signal is suppressed in a selectable or given cycle and all the other clock pulses in the cycle are taken over in the second clock signal.
摘要翻译： 延迟装置包括布置在至少两排4,5中的存储元件; 6,7集成电路中，最好采用开关电容技术。 延迟装置2; 3具有偶数个存储元件。 提供第一时钟信号，为了产生等于第一时钟信号的时钟周期的奇数倍的延迟时间，通过时钟产生电路9导出第二时钟信号，该第二时钟信号使时钟信号 存储元件并且以这样的方式从第一时钟信号导出，使得第一时钟信号的一个时钟脉冲在可选择或给定的周期中被抑制，并且周期中的所有其他时钟脉冲在第二时钟信号中被接管。
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公开(公告)号：US5933198A
公开(公告)日：1999-08-03
申请号：US798345
申请日：1997-02-10
申请人： Sonke Struck , Ole Steinfatt
发明人： Sonke Struck , Ole Steinfatt
CPC分类号： H03H17/0251 , H04N9/646
摘要： For activating or deactivating the comb filter function with pixel precision, a comb filter arrangement including a delay circuit (3) and a first matching circuit (1) having at least two storage cells, these circuits receive a picture signal, having a sequence of individual pixels applied to the comb filter arrangement. The output signals of the delay circuit and the first matching circuit are superposed by a superposition stage (4) supplying a filtered picture signal from its output. The matching circuit (1) is implemented in such a way that it gives the picture signal applied thereto substantially the same amplitude variations as the delay circuit (3), and that the difference between the delay of the output signals from the delay circuit (3) and the matching circuit (1) corresponds to a nominal value. The comb filter arrangement further includes a second matching circuit (2) and a switching circuit (6), the unfiltered picture signal being applied to the input of the second matching circuit (2) which gives the picture signal substantially the same amplitude variations and delays as the first matching circuit (1), and the switching circuit, for switching the comb filter function on and off, alternately deactivating either the second matching circuit (2) or the delay circuit (3).
摘要翻译： 为了以像素精度激活或去激活梳状滤波器功能，包括具有至少两个存储单元的延迟电路（3）和第一匹配电路（1）的梳状滤波器装置，这些电路接收具有个体序列的图像信号 施加到梳状滤波器装置的像素。 延迟电路和第一匹配电路的输出信号通过从其输出端提供滤波后的图像信号的叠加级（4）叠加。 匹配电路（1）以这样一种方式实现，使得其施加的图像信号基本上与延迟电路（3）相同的幅度变化，并且来自延迟电路（3）的输出信号的延迟之间的差 ），并且匹配电路（1）对应于标称值。 梳状滤波器装置还包括第二匹配电路（2）和开关电路（6），未滤波的图像信号被施加到第二匹配电路（2）的输入端，其给予图像信号基本相同的幅度变化和延迟 作为第一匹配电路（1）和用于切换梳状滤波器功能的开关电路，交替地去激活第二匹配电路（2）或延迟电路（3）。
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公开(公告)号：US5953480A
公开(公告)日：1999-09-14
申请号：US678216
申请日：1996-07-11
摘要： A comb filter arrangement comprising at least one delay circuit and an adder, this adder being twice supplied with a video signal modulated on a carrier, which video signals are applied mutually shifted with time. The signals are delayed by the delay circuits, so that either video signal applied to the adder is delayed relative to the other video signal by a given period of time. Furthermore, the delay circuits are arranged in switched capacitor technique.
摘要翻译： 一种包括至少一个延迟电路和加法器的梳状滤波器装置，该加法器被两次提供在载波上调制的视频信号，这些视频信号被施加相互随时间移位。 信号由延迟电路延迟，使得施加到加法器的任一视频信号相对于另一个视频信号延迟给定的时间段。 此外，延迟电路以开关电容器技术布置。
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公开(公告)号：US5661679A
公开(公告)日：1997-08-26
申请号：US595090
申请日：1996-02-01
申请人： Sonke Struck
发明人： Sonke Struck
CPC分类号： G11C27/04
摘要： A delay circuit having at least two memory cells (3, 4, 5, 6, 8, 9) each including a capacitive memory element (20, 26, 40, 45), a write transistor (22, 28, 42, 47) by which information to be delayed can be written from a write line (18) into the capacitive memory element (20, 26, 40, 45), and a read transistor (21, 27, 41, 46) by which information can be read from the capacitive memory element (20, 26, 40, 45) on a read line (19), and having a control arrangement which is clocked by means of a first control clock and whose input receives a control signal and which includes intercoupled control circuits (11, 12, 13, 14, 15, 16) one of which is associated with a respective memory cell (3, 4, 5, 6, 8, 9), each control circuit (11, 12, 13, 14, 15, 16) of the read transistor (21, 27, 41, 46) of the associated memory cell (3, 4, 5, 6, 8, 9) being controllable by means of the input signal and each control circuit (11, 12, 13, 14, 15, 16) of the write transistor (22, 28, 42, 47) of the associated memory cell being controllable by means of the output signal, in which each control circuit (11, 12, 13, 14, 15, 16) has a first control element (43, 48, 24, 30) and a subsequent second control element (44, 49, 25, 31), those control circuits (14) whose preceding control circuit (11) is arranged locally remote have a third control element (29) preceding the first control element (30), in that the input of the third control element (29) receives the output signal of the first control element (24) of the preceding, spatially remote control circuit (11), and in that the first control elements (43, 48, 24, 30) of the control circuits (11, 12, 13, 14, 15, 16) are clocked by the first clock and the second (44, 49, 25, 31) and third (29) control elements of the control circuits (11, 12, 13, 14, 15, 16) are clocked by a second clock.
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