摘要:
A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.
摘要:
The configurations and adjusting method of a successive approximation analog-to-digital converter (SAR ADC) are provided. The provided SAR ADC includes at least one capacitor with a first and a second terminals, and a plurality of bits, each of which is connected to the at least one capacitor, wherein the first terminal receives an input signal, and the second terminal selectively receives one of a first and a second reference voltages, and a first comparator receiving an adjustable third reference voltage and a first voltage value generated by the input signal, wherein a connection of the second terminal of each the capacitor of the capacitor array is switched when the first voltage value is larger than the third reference voltage.
摘要:
The configurations and adjusting method of a successive approximation analog-to-digital converter (SAR ADC) are provided. The provided SAR ADC includes at least one capacitor with a first and a second terminals, and a plurality of bits, each of which is connected to the at least one capacitor, wherein the first terminal receives an input signal, and the second terminal selectively receives one of a first and a second reference voltages, and a first comparator receiving an adjustable third reference voltage and a first voltage value generated by the input signal, wherein a connection of the second terminal of each the capacitor of the capacitor array is switched when the first voltage value is larger than the third reference voltage.
摘要:
A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.
摘要:
A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.
摘要:
A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.
摘要:
A metal-oxide-metal (MOM) capacitor able to reduce area of capacitor arrays is revealed. The MOM capacitor mainly includes at least three parallel conducting layers. Each parallel conducting layer consists of a first conductive plate, a second conductive plate disposed around the first conductive plate. There is a preset distance between the first conductive plate and the second conductive plate. The first conductive plates are electrically connected by at least one first via while the second conductive plates are electrically connected by at least one second via. Thereby, while being applied to capacitor arrays, the second conductive plates of the two adjacent MOM capacitors are connected together and shared with each other, so as to significantly reduce area of the capacitor array, improve circuit density and further optimize the layout efficiency of the chip design.