公开(公告)号：US08643529B2

公开(公告)日：2014-02-04

申请号：US13488544

申请日：2012-06-05

申请人： Jin-Fu Lin

发明人： Jin-Fu Lin

IPC分类号： H03M1/12

CPC分类号： H03M1/164 ,  H03M1/46

摘要： A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other.

摘要翻译： 一种用于操作SAR辅助流水线模数转换器的方法，包括：在当前级电路中启用SAR ADC，以便在第一时间间隔期间将输入模拟电压转换为数字代码，在第一时间段期间复位当前级电路中的MDAC的运算放大器 时间间隔，将当前级电路的SAR ADC保持在使能状态，以在第二时间间隔期间输出，并且在第二时间间隔期间启用当前级电路中的MDAC。 该方法还包括使得当前级电路中的SAR ADC在第三时间间隔期间进行采样，并且在第三时间间隔期间将当前级电路中的MDAC的输出端连接到下一级电路的输入端。 第一，第二和第三时间间隔是连续的，并且彼此不重叠。

公开(公告)号：US20130321184A1

公开(公告)日：2013-12-05

申请号：US13488544

申请日：2012-06-05

申请人： Jin-Fu Lin

发明人： Jin-Fu Lin

IPC分类号： H03M1/38

CPC分类号： H03M1/164 ,  H03M1/46

摘要： A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other.

摘要翻译： 一种用于操作SAR辅助流水线模数转换器的方法，包括：在当前级电路中启用SAR ADC，以便在第一时间间隔期间将输入模拟电压转换为数字代码，在第一时间段期间复位当前级电路中的MDAC的运算放大器 时间间隔，将当前级电路的SAR ADC保持在使能状态，以在第二时间间隔期间输出，并且在第二时间间隔期间启用当前级电路中的MDAC。 该方法还包括使得当前级电路中的SAR ADC在第三时间间隔期间进行采样，并且在第三时间间隔期间将当前级电路中的MDAC的输出端连接到下一级电路的输入端。 第一，第二和第三时间间隔是连续的，并且彼此不重叠。

公开(公告)号：US08390501B2

公开(公告)日：2013-03-05

申请号：US13096908

申请日：2011-04-28

申请人： Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

发明人： Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC分类号： H03M1/34

CPC分类号： H03M1/462 ,  H03M1/466

摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

摘要翻译： 公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 第一和第二电容器DAC分别接收第一和第二输入信号。 第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，精细比较器将第一电容器DAC的输出与 第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。 当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过至少一个SAR模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

公开(公告)号：US08299952B1

公开(公告)日：2012-10-30

申请号：US13093649

申请日：2011-04-25

申请人： Jin-Fu Lin ,  Chia-Hsuan Huang

发明人： Jin-Fu Lin ,  Chia-Hsuan Huang

IPC分类号： H03M1/12

CPC分类号： H03K5/00 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45986 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/442

摘要： A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.

摘要翻译： 提供了包括第一采样电容器，第二采样电容器，运算放大器，第三电容器和第四电容器的开关电容器电路。 第一采样电容器设置成在采样阶段对输入信号进行采样。 第二采样电容器设置成在采样阶段对输入信号进行采样。 其中，在第一放大相位中，第三电容器存储运算放大器的偏移电压，第四电容器存储从第一采样电容器和第二采样电容器流出的电荷，并且在第二放大相位中， 第四电容器将存储的电荷返回到第一采样电容器和第二采样电容器。

公开(公告)号：US08217819B2

公开(公告)日：2012-07-10

申请号：US12941510

申请日：2010-11-08

申请人： Soon-Jyh Chang ,  Jin-Fu Lin

发明人： Soon-Jyh Chang ,  Jin-Fu Lin

IPC分类号： H03M1/66

CPC分类号： H03M1/0653 ,  H03M1/806

摘要： The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.

摘要翻译： 本发明涉及一种乘法数模转换器（MDAC）及其方法。 电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。 每个电容器由至少两个子电容器组成。 电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。 排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化被平均化。

公开(公告)号：US20140049872A1

公开(公告)日：2014-02-20

申请号：US13587319

申请日：2012-08-16

申请人： Guan-Ying Huang ,  Jin-Fu Lin

发明人： Guan-Ying Huang ,  Jin-Fu Lin

IPC分类号： H01G4/30

CPC分类号： H01G4/30 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5225 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-oxide-metal (MOM) capacitor able to reduce area of capacitor arrays is revealed. The MOM capacitor mainly includes at least three parallel conducting layers. Each parallel conducting layer consists of a first conductive plate, a second conductive plate disposed around the first conductive plate. There is a preset distance between the first conductive plate and the second conductive plate. The first conductive plates are electrically connected by at least one first via while the second conductive plates are electrically connected by at least one second via. Thereby, while being applied to capacitor arrays, the second conductive plates of the two adjacent MOM capacitors are connected together and shared with each other, so as to significantly reduce area of the capacitor array, improve circuit density and further optimize the layout efficiency of the chip design.

摘要翻译： 揭示了能够减小电容器阵列面积的金属氧化物金属（MOM）电容器。 MOM电容器主要包括至少三个平行导电层。 每个平行导电层由第一导电板，围绕第一导电板设置的第二导电板组成。 在第一导电板和第二导电板之间存在预设的距离。 第一导电板通过至少一个第一通孔电连接，而第二导电板通过至少一个第二通孔电连接。 因此，在将电容器阵列施加到电容器阵列的同时，两个相邻的MOM电容器的第二导电板彼此连接并共享，从而显着地减小电容器阵列的面积，从而提高电路密度并进一步优化布线效率 芯片设计。

公开(公告)号：US20130285843A1

公开(公告)日：2013-10-31

申请号：US13455515

申请日：2012-04-25

申请人： Jin-Fu LIN

发明人： Jin-Fu LIN

IPC分类号： H03M1/38

CPC分类号： H03M1/144

摘要： A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

摘要翻译： 主数字模拟转换器（DAC）接收至少一个输入并产生经调整的输入。 SAR单元基于接收经调整的输入的比较单元的比较输出产生用于控制主DAC的代码。 参考发生器在产生的代码的控制下产生至少一个参考电压，然后在每个相应周期中转发给比较单元，用于定义每个周期的搜索范围，其中后者的参考电压的绝对值 周期小于前一周期的参考电压，使得后一周期的搜索范围小于前一周期的搜索范围，并且所有周期的搜索范围以基极电压为中心。

公开(公告)号：US08493260B2

公开(公告)日：2013-07-23

申请号：US13240806

申请日：2011-09-22

申请人： Yuan-Kai Chu ,  Jin-Fu Lin

发明人： Yuan-Kai Chu ,  Jin-Fu Lin

IPC分类号： H03M1/14

CPC分类号： H03M1/14

摘要： A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

摘要翻译： 用于在转换阶段将模拟输入转换成N位数字输出的SAR ADC包括：三个比较器，每两个电容器子阵列分别耦合到三个比较器，其中使用两个电容器子阵列 用于对模拟输入进行采样并为相应的比较器提供两个输入; 以及耦合到三个比较器和三个电容器阵列的SAR逻辑，用于在每个转换子相中，将每个电容器子阵列的两个选定的电容器耦合到一组确定的参考电平，耦合两个选择的电容器 在前一转换子阶段中，将每个电容器子阵列转换成基于在前一转换子相中从三个比较器输出的一组数据而获得的一组调整参考电平，然后产生N位的两位， 通过对从三个比较器输出的一组数据进行编码来进行位数字输出。

公开(公告)号：US08451151B2

公开(公告)日：2013-05-28

申请号：US13210229

申请日：2011-08-15

申请人： Jin-Fu Lin

发明人： Jin-Fu Lin

IPC分类号： H03M1/00

CPC分类号： H03M1/1061 ,  H03M1/468 ,  H03M1/804

摘要： A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.

摘要翻译： 提供了包括至少一个电容器阵列的逐次逼近寄存器ADC的电容失配校准方法。 该方法包括以下步骤：首先配置至少两个补偿电容器。 选择来自电容器阵列的电容器作为待测电容器。 然后，确定电容器阵列的端子和补偿电容器的端子上的端子电压。 基于确定的端子电压输出第一比较电压。 之后，基于第一比较电压和第二比较电压来控制比较序列，以输出相应的数字位序列。 最后，计算校准值，以根据数字位校准待测电容器的值。

公开(公告)号：US20130073048A1

公开(公告)日：2013-03-21

申请号：US13677205

申请日：2012-11-14

申请人： Jin-Fu Lin ,  Li-Chiu Lin

发明人： Jin-Fu LIN

IPC分类号： A61F2/44

CPC分类号： A61F2/44 ,  A61B17/7059 ,  A61F2/4465 ,  A61F2002/30281 ,  A61F2002/30507 ,  A61F2002/30576 ,  A61F2002/30594 ,  A61F2002/30604 ,  A61F2002/30777 ,  A61F2002/30785 ,  A61F2002/30848 ,  A61F2002/30884 ,  A61F2002/30899 ,  A61F2002/30904 ,  A61F2310/00023

摘要： A positioning insert for two adjacent vertebral bodies includes a plate like insert adapted to fix relative positions of the two adjacent vertebral bodies and provided with a sharp edge oppositely formed relative to the dull side and first holes defined through a side face of the plate like insert, wherein the sharp edge is formed to have an angle between 5 to 15 degrees; and an annular insert adapted to be inserted into a space between the two adjacent vertebral bodies and having second holes and a slot defined in a peripheral side face thereof to accommodate the plate like insert so as to have the plate like insert received in the slot.

摘要翻译： 用于两个相邻的椎体的定位插入件包括板状插入件，其适于固定两个相邻的椎体的相对位置，并且设置有相对于钝的侧面相反地形成的尖锐边缘，以及通过板状插入物的侧面限定的第一孔 ，其中所述锋利边缘形成为具有5至15度之间的角度; 以及环形插入件，其适于插入到两个相邻的椎骨体之间的空间中，并且具有限定在其周边侧面中的第二孔和狭槽以容纳板状插入物，以使得板状插入件容纳在狭槽中。