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11 条记录 (耗时 0.032 秒)

    Semiconductor device with partial passivation layer
    2.
    发明授权
    Semiconductor device with partial passivation layer 有权
    具有部分钝化层的半导体器件

    公开(公告)号：US06313538B1

    公开(公告)日：2001-11-06

    申请号：US09489479

    申请日：2000-01-21

    申请人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    发明人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.

    摘要翻译： 半导体器件包括第一电介质层，形成在第一电介质层中的多个导电互连，形成在导电互连之上的图案化钝化层，以及形成在钝化层和第一介电层上方并与钝化层接触的第二介电层 。 一种用于形成半导体器件的方法包括提供基底层，在基底层上形成第一介电层，在第一介电层中形成多个导电互连，在导电互连之上形成图案化的钝化层，以及形成第二电介质 并且与钝化层和第一介电层接触。

    Method of forming a semiconductor device with metal silicide regions
    3.
    发明授权
    Method of forming a semiconductor device with metal silicide regions 有权
    用金属硅化物区形成半导体器件的方法

    公开(公告)号：US06268255B1

    公开(公告)日：2001-07-31

    申请号：US09479402

    申请日：2000-01-06

    申请人： Paul R. Besser ,  Christian Zistl ,  Nicholas J. Kepler

    发明人： Paul R. Besser ,  Christian Zistl ,  Nicholas J. Kepler

    IPC分类号： H01L21336

    CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L29/6659

    摘要： The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon, forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.

    摘要翻译： 本发明涉及制造半导体器件的方法。 在一个说明性实施例中，该方法包括形成由多晶硅组成的第一层，在多晶硅层上形成由难熔金属组成的第二层，并将第二层的至少一部分转化为第一金属硅化物。 该方法还包括在难熔金属层或第一金属硅化物层之上形成抗反射涂层，以及对第一金属硅化物层和多晶硅层进行构图以限定由第一金属硅化物区和 多晶硅层，在衬底中形成多个源极/漏极区域，在至少栅极堆叠和源极/漏极区域上形成由难熔金属组成的第三层，并将第三层的至少一部分转化为 第二金属硅化物区域。

    Method and test structure for characterizing sidewall damage in a semiconductor device
    4.
    发明授权
    Method and test structure for characterizing sidewall damage in a semiconductor device 失效
    用于表征半导体器件中侧壁损伤的方法和测试结构

    公开(公告)号：US06600333B1

    公开(公告)日：2003-07-29

    申请号：US09501958

    申请日：2000-02-10

    申请人： Jeremy I. Martin ,  Nicholas J. Kepler ,  Larry L. Zhao

    发明人： Jeremy I. Martin ,  Nicholas J. Kepler ,  Larry L. Zhao

    IPC分类号： G01R2726

    CPC分类号： H01L22/34 ,  G01R31/2884

    摘要： A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared. Damage to the insulative layer is characterized based on the comparison.

    摘要翻译： 测试电路包括晶片，形成在晶片上的绝缘层，以及形成在绝缘层中的多个测试结构。 每个测试结构包括具有第一多个指状物的第一梳子和具有第二多个指状物的第二梳子。 手指的第一和第二多个交织以限定第一和第二多个手指之间的手指间隔。 测试结构中第一个测试结构中的手指间距不同于第二个测试结构中的手指间距。 用于表征半导体器件中的损伤的方法包括提供具有绝缘层的晶片和形成在绝缘层中的多个测试结构。 测试结构具有不同的几何形状。 确定多个测试结构的第一和第二测试结构的电特性。 比较第一和第二测试结构的电气特性。 基于比较，对绝缘层的损伤进行了表征。

    Method for self-aligning polysilicon gates with field isolation and the resultant structure
    7.
    发明授权
    Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效
    使用场隔离自对准多晶硅栅极的方法及其结果

    公开(公告)号：US6046088A

    公开(公告)日：2000-04-04

    申请号：US985400

    申请日：1997-12-05

    申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/6659

    摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

    摘要翻译： 在诸如浅​​氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。