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    Dual slurry particle sizes for reducing microscratching of wafers
    4.
    发明授权
    Dual slurry particle sizes for reducing microscratching of wafers 有权
    用于减少晶片显微镜的双重浆料粒径

    公开(公告)号：US06294472B1

    公开(公告)日：2001-09-25

    申请号：US09576750

    申请日：2000-05-23

    申请人： Jonathan B. Smith ,  Paul R. Besser ,  Jeremy I. Martin

    发明人： Jonathan B. Smith ,  Paul R. Besser ,  Jeremy I. Martin

    IPC分类号： H01L2100

    CPC分类号： C09G1/02 ,  B24B37/044 ,  B24B57/02 ,  H01L21/30625

    摘要： A method includes providing at least one wafer having a process layer formed thereon for polishing. The process layer is polished using a first polishing process that is associated with a slurry having a first abrasive particle size. The process layer is polished using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size. A system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon for polishing. The polishing tool is adapted to polish the process layer using a first polishing process that is associated with a slurry having a first abrasive particle size. The polishing tool is adapted to polish the process layer using a second polishing process that is associated with a slurry having a second abrasive particle size that is different from the first abrasive particle size. The process controller is coupled to the polishing tool and adapted to communicate with at least one of a slurry controller and the polishing tool.

    摘要翻译： 一种方法包括提供至少一个晶片，其上形成有用于抛光的工艺层。 使用与具有第一研磨粒度的浆料相关联的第一抛光工艺来抛光工艺层。 使用与具有不同于第一磨料颗粒尺寸的第二磨料颗粒尺寸的浆料相关联的第二抛光方法来抛光工艺层。 系统包括抛光工具和过程控制器。 抛光工具适于接收至少一个晶片，其上形成有用于抛光的工艺层。 抛光工具适于使用与具有第一研磨粒度的浆料相关联的第一抛光工艺来抛光工艺层。 抛光工具适于使用与具有不同于第一磨料颗粒尺寸的第二磨料颗粒尺寸的浆料相关联的第二抛光工艺来抛光工艺层。 过程控制器耦合到抛光工具并且适于与浆料控制器和抛光工具中的至少一个连通。

    Copper damascene with low-k capping layer and improved electromigration reliability
    6.
    发明授权
    Copper damascene with low-k capping layer and improved electromigration reliability 有权
    具有低k覆盖层的铜镶嵌和改善的电迁移可靠性

    公开(公告)号：US06989601B1

    公开(公告)日：2006-01-24

    申请号：US10946071

    申请日：2004-09-22

    申请人： Minh van Ngo ,  Jeremy I. Martin ,  Hartmut Ruelke

    发明人： Minh van Ngo ,  Jeremy I. Martin ,  Hartmut Ruelke

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/931

    摘要： The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

    摘要翻译： 通过在其上沉积低k覆盖层，例如具有约4.5至约5.5的介电常数的碳化硅覆盖层，Cu线的电迁移电阻显着提高。 实施方案包括用包含用N 2 N 2稀释的NH 3的等离子体依次处理镶嵌的Cu的暴露的平坦化表面，停止等离子体和NH 3的流动 >和N 2 2，泵出室; 引入三甲基硅烷NH 3和He，引发PECVD以沉积碳化硅覆盖层，厚度为约至约800。 实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

    Copper damascene with low-k capping layer and improved electromigration reliability
    8.
    发明授权
    Copper damascene with low-k capping layer and improved electromigration reliability 失效
    具有低k覆盖层的铜镶嵌和改善的电迁移可靠性

    公开(公告)号：US06797652B1

    公开(公告)日：2004-09-28

    申请号：US10097965

    申请日：2002-03-15

    申请人： Minh van Ngo ,  Jeremy I. Martin ,  Hartmut Ruelke

    发明人： Minh van Ngo ,  Jeremy I. Martin ,  Hartmut Ruelke

    IPC分类号： H01L2100

    CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/931

    摘要： The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

    摘要翻译： 通过在其上沉积低k覆盖层，例如具有约4.5至约5.5的介电常数的碳化硅覆盖层，Cu线的电迁移电阻显着提高。 实施方案包括用包含用N 2稀释的NH 3的等离子体依次处理嵌入的Cu的平坦化表面，停止等离子体和NH 3和N 2的流动，泵出室; 引入三甲基硅烷，NH 3和He，引发PECVD以沉积碳化硅覆盖层，厚度为约至约800。 实施例还包括形成在介电常数（k）小于约3.9的电介质材料中的Cu双镶嵌结构。

    Method and test structure for characterizing sidewall damage in a semiconductor device
    9.
    发明授权
    Method and test structure for characterizing sidewall damage in a semiconductor device 失效
    用于表征半导体器件中侧壁损伤的方法和测试结构

    公开(公告)号：US06600333B1

    公开(公告)日：2003-07-29

    申请号：US09501958

    申请日：2000-02-10

    申请人： Jeremy I. Martin ,  Nicholas J. Kepler ,  Larry L. Zhao

    发明人： Jeremy I. Martin ,  Nicholas J. Kepler ,  Larry L. Zhao

    IPC分类号： G01R2726

    CPC分类号： H01L22/34 ,  G01R31/2884

    摘要： A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared. Damage to the insulative layer is characterized based on the comparison.

    摘要翻译： 测试电路包括晶片，形成在晶片上的绝缘层，以及形成在绝缘层中的多个测试结构。 每个测试结构包括具有第一多个指状物的第一梳子和具有第二多个指状物的第二梳子。 手指的第一和第二多个交织以限定第一和第二多个手指之间的手指间隔。 测试结构中第一个测试结构中的手指间距不同于第二个测试结构中的手指间距。 用于表征半导体器件中的损伤的方法包括提供具有绝缘层的晶片和形成在绝缘层中的多个测试结构。 测试结构具有不同的几何形状。 确定多个测试结构的第一和第二测试结构的电特性。 比较第一和第二测试结构的电气特性。 基于比较，对绝缘层的损伤进行了表征。