-
公开(公告)号：US20050224874A1
公开(公告)日：2005-10-13
申请号：US11148805
申请日：2005-06-09
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833 , Y10S438/91
摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.
-
公开(公告)号：US20050118792A1
公开(公告)日：2005-06-02
申请号：US10725977
申请日：2003-12-01
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833 , Y10S438/91
摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.
-
公开(公告)号：US20070218662A1
公开(公告)日：2007-09-20
申请号：US11725927
申请日：2007-03-20
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L29/6653 , H01L29/7833
摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.
摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。
-
公开(公告)号：US20090170256A1
公开(公告)日：2009-07-02
申请号：US12206456
申请日：2008-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/268 , H01L21/2686 , H01L21/324 , H01L21/823807 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.
摘要翻译： 一种形成晶体管的方法，包括在n型半导体本体上形成栅极结构，并形成与半导体本体中的栅极结构基本对准的凹槽。 然后在凹槽中外延生长硅锗，并在硅锗上形成硅帽层。 在该方法中包括将杂质进一步引入硅锗以增加其熔点并在半导体本体中注入p型源/漏区。 该方法的结论是进行高温热处理。
-
5.发明申请Interface improvement by stress application during oxide growth through use of backside films 有权通过使用背面薄膜在氧化物生长期间的应力应用的界面改善公开(公告)号：US20050208776A1
公开(公告)日：2005-09-22
申请号：US11083912
申请日：2005-03-18
IPC分类号： H01L21/28 , H01L21/316 , H01L21/318 , H01L21/469 , H01L21/8234 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/7842 , H01L21/0217 , H01L21/02211 , H01L21/02233 , H01L21/02255 , H01L21/02274 , H01L21/28211 , H01L21/31662 , H01L21/3185 , H01L21/823462 , H01L21/823857 , H01L29/7833
摘要： The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.
摘要翻译： 本发明在一个方面提供了一种在微电子衬底上制造栅氧化层的方法。 该实施例包括在微电子晶片的背面上形成应力诱导图案，并且在由应力诱导图案引起的拉伸应力的存在下，在微电子晶片的正面上生长栅极氧化物层。
-
公开(公告)号：US07670892B2
公开(公告)日：2010-03-02
申请号：US11268040
申请日：2005-11-07
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.
摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。
-
公开(公告)号：US07572716B2
公开(公告)日：2009-08-11
申请号：US11739981
申请日：2007-04-25
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/324
摘要： A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal. The disclosure also pertains to semiconductor components produced in this manner, and various embodiments and improvements of such methods for producing such components.
摘要翻译： 公开了一种用于将诸如晶体管的源极或漏极区域的半导体衬底的目标区域掺杂到电子有源掺杂剂（例如用于在NMOS器件中产生有源区域的N型掺杂剂）或P 用于在PMOS器件中产生有源区）的具有良好控制的放置曲线和强激活。 该方法包括将目标区域中的含碳扩散抑制剂置于掺杂剂浓度的约50％处，并使掺杂剂活化约1,040摄氏度的热退火。 在许多情况下，在这样高的温度下的热退火引起掺杂剂离开目标区域的过度扩散，但这种相对浓度的碳在这样的高温热退火期间产生了掺杂剂扩散的意外的减少。 本公开还涉及以这种方式制造的半导体部件，以及用于制造这种部件的这种方法的各种实施例和改进。
-
8.发明授权Interface improvement by stress application during oxide growth through use of backside films 有权通过使用背面薄膜在氧化物生长期间的应力应用的界面改善公开(公告)号：US07208380B2
公开(公告)日：2007-04-24
申请号：US11083912
申请日：2005-03-18
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/0217 , H01L21/02211 , H01L21/02233 , H01L21/02255 , H01L21/02274 , H01L21/28211 , H01L21/31662 , H01L21/3185 , H01L21/823462 , H01L21/823857 , H01L29/7833
摘要： The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.
摘要翻译： 本发明在一个方面提供了一种在微电子衬底上制造栅氧化层的方法。 该实施例包括在微电子晶片的背面上形成应力诱导图案，并且在由应力诱导图案引起的拉伸应力的存在下，在微电子晶片的正面上生长栅极氧化物层。
-
公开(公告)号：US07795122B2
公开(公告)日：2010-09-14
申请号：US11725927
申请日：2007-03-20
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L29/6653 , H01L29/7833
摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.
摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。
-
公开(公告)号：US07129127B2
公开(公告)日：2006-10-31
申请号：US10950138
申请日：2004-09-24
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220). A poly cap layer is formed over the device (222) and an anneal or other thermal process is performed (224) that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.
-
-
-
-
-
-
-
-
-
搜索结果
55 条记录 (耗时 0.02 秒)
