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公开(公告)号：US20120142300A1
公开(公告)日：2012-06-07
申请号：US12957507
申请日：2010-12-01
申请人： Stefan Herzinger , Volker Neubauer
发明人： Stefan Herzinger , Volker Neubauer
IPC分类号： H04W88/02
CPC分类号： H04B1/26 , H04B1/0064 , H04L27/3854 , H04L27/3872
摘要： Some embodiments of the present disclosure relate to multiband receivers that include at least one divider unit having a divisor that is other-than-two. For example, in some embodiments the divisor is an odd integer (e.g., three). Such divisors allow oscillators for respective receiver subunits in a multi-band receiver to have frequencies that are sufficiently different from one another so as to limit cross-talk interference there between, even when the receiver subunits are concurrently receiving data on adjacent channels. To facilitate this other-than-two divisor, a phase error compensation block is often used to compensate for the effects of using the other-than-two divisor.
摘要翻译： 本公开的一些实施例涉及多频带接收机，其包括至少一个具有不同于二的除数的除法器单元。 例如，在一些实施例中，除数是奇整数（例如，三个）。 这样的除数允许多频带接收机中的相应接收器子单元的振荡器具有彼此充分不同的频率，以便即使当接收机子单元同时在相邻信道上接收数据时也限制其间的串扰干扰。 为了方便这个除二分之一以外，通常使用相位误差补偿块来补偿使用其他二除数的影响。
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公开(公告)号：US08983413B2
公开(公告)日：2015-03-17
申请号：US12957507
申请日：2010-12-01
申请人： Stefan Herzinger , Volker Neubauer
发明人： Stefan Herzinger , Volker Neubauer
CPC分类号： H04B1/26 , H04B1/0064 , H04L27/3854 , H04L27/3872
摘要： Some embodiments of the present disclosure relate to multiband receivers that include at least one divider unit having a divisor that is other-than-two. For example, in some embodiments the divisor is an odd integer (e.g., three). Such divisors allow oscillators for respective receiver subunits in a multi-band receiver to have frequencies that are sufficiently different from one another so as to limit cross-talk interference there between, even when the receiver subunits are concurrently receiving data on adjacent channels. To facilitate this other-than-two divisor, a phase error compensation block is often used to compensate for the effects of using the other-than-two divisor.
摘要翻译： 本公开的一些实施例涉及多频带接收机，其包括至少一个具有不同于二的除数的除法器单元。 例如，在一些实施例中，除数是奇整数（例如，三个）。 这样的除数允许多频带接收机中的相应接收器子单元的振荡器具有彼此充分不同的频率，以便即使当接收机子单元同时在相邻信道上接收数据时也限制其间的串扰干扰。 为了方便这个除二分之一以外，通常使用相位误差补偿块来补偿使用其他二除数的影响。
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3.发明授权Phase/frequency detector, phase locked loop, method for phase/frequency detection and method for generating an oscillator signal 有权相位/频率检测器，锁相环，相位/频率检测方法以及产生振荡器信号的方法公开(公告)号：US07592874B2
公开(公告)日：2009-09-22
申请号：US11925539
申请日：2007-10-26
CPC分类号： H03L7/085 , H03D13/001 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.
摘要翻译： 相位/频率检测器具有模计数器，用于根据振荡器信号输出具有预定字长的计数器字。 另外，提供了用于输出具有作为通道字的积分的函数的预定字长的积分器字的模积分器。 相位/频率检测器还具有差分元件，用于输出具有预定字长的相位误差字作为计数器字和积分器字之差的函数。
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公开(公告)号：US07420485B2
公开(公告)日：2008-09-02
申请号：US11726844
申请日：2007-03-23
IPC分类号： H03M3/00
CPC分类号： H03M7/3015
摘要： A sigma-delta modulator is supplied with a data word and includes a first and at least one further modulation stage, each having at least two adders. The adders in the first modulation stage process a low-significance component and a delayed more significant component of the data word and provide a result word and a carry at their respective outputs. The adders in the at least one further modulation stage process a low-significance component and a more significant component of the result word and provide a further result word and a carry at their respective outputs. The low-significance component and the more significant component of the result word are provided to the further modulation stages with an unvarying delay. A bit stream is derived from a carry from final instances of the at least two adders in the first modulation stage and in the further modulation stage respectively.
摘要翻译： Σ-Δ调制器被提供有数据字，并且包括第一和至少一个另外的调制级，每个具有至少两个加法器。 第一调制级中的加法器处理数据字的低有效分量和延迟更高有效分量，并在其各自的输出端提供结果字和进位。 所述至少一个另外的调制级中的加法器处理结果字的低有效分量和更重要的分量，并在其各自的输出端提供另外的结果字和进位。 结果字的低有效分量和更重要的分量被提供给具有不变延迟的进一步的调制阶段。 从第一调制阶段和另外的调制阶段的至少两个加法器的最终实例的进位分别导出比特流。
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5.发明申请PHASE/FREQUENCY DETECTOR, PHASE LOCKED LOOP, METHOD FOR PHASE/FREQUENCY DETECTION AND METHOD FOR GENERATING AN OSCILLATOR SIGNAL 有权相位/频率检测器，相位锁定环路，相位/频率检测方法及产生振荡器信号的方法公开(公告)号：US20080100386A1
公开(公告)日：2008-05-01
申请号：US11925539
申请日：2007-10-26
CPC分类号： H03L7/085 , H03D13/001 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.
摘要翻译： 相位/频率检测器具有模计数器，用于根据振荡器信号输出具有预定字长的计数器字。 另外，提供了用于输出具有作为通道字的积分的函数的预定字长的积分器字的模积分器。 相位/频率检测器还具有差分元件，用于输出具有预定字长的相位误差字作为计数器字和积分器字之差的函数。
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6.发明申请公开(公告)号：US20070222526A1
公开(公告)日：2007-09-27
申请号：US11401393
申请日：2006-04-10
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03L7/099 , H03L7/18 , H03L2207/06
摘要： A digitally controlled oscillator device includes a programming input, a selection input and an oscillator core with a first capacitive element which is frequency determining and programmable. The first capacitive element is coupled to the programming input that receives a first data word by which an oscillating frequency of the oscillator device is programmed with a predetermined frequency step size. The oscillator device further includes a selection unit for selecting a mode which is coupled to the selection input that receives a mode selection signal. The mode is selectable from a plurality of modes depending on the mode selection signal and each mode from the plurality of modes is characterized by a predetermined frequency step size. The digitally controlled oscillator device also includes a deattenuation amplifier.
摘要翻译： 数字控制振荡器装置包括编程输入，选择输入和具有频率确定和可编程的第一电容元件的振荡器芯。 第一电容元件耦合到接收第一数据字的编程输入，通过该第一数据字，振荡器器件的振荡频率以预定频率步长编程。 振荡器装置还包括选择单元，用于选择耦合到接收模式选择信号的选择输入的模式。 该模式可以根据模式选择信号从多个模式中选择，并且来自多个模式的每个模式的特征在于预定的频率步长。 数字控制振荡器装置还包括去衰减放大器。
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公开(公告)号：US20060145743A1
公开(公告)日：2006-07-06
申请号：US11293381
申请日：2005-12-02
申请人： Volker Neubauer
发明人： Volker Neubauer
IPC分类号： H03K3/289
CPC分类号： H03K3/012 , H03K3/00 , H03K3/35625 , H03K17/00
摘要： A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data input, and it is coupled via a first switching device to the supply connection, and via a second switching device to the reference ground potential connection. Furthermore, a first multivibrator circuit having transistors of a first conductance type is provided, and is coupled to the supply connection. A second multivibrator circuit having transistors of a second conductance type is coupled to the reference ground potential connection. The transistors in the first and second multivibrator circuits in the data latch are connected to one another on the output side at a first node and at a second node, with the first node being connected to one output of the inverter, and the second node forming an output tap.
摘要翻译： 数据锁存器包含供电连接，参考地电位连接和数据输入。 逆变器的输入端连接到数据输入端，并通过第一开关器件耦合到电源连接，并通过第二开关器件耦合到参考地电位连接。 此外，提供具有第一电导型晶体管的第一多谐振荡器电路，并且耦合到电源连接。 具有第二电导型晶体管的第二多谐振荡器电路耦合到参考地电位连接。 数据锁存器中的第一和第二多谐振荡器电路中的晶体管在第一节点和第二节点处的输出侧彼此连接，第一节点连接到逆变器的一个输出端，第二节点形成 输出水龙头。
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公开(公告)号：US08098104B2
公开(公告)日：2012-01-17
申请号：US12578105
申请日：2009-10-13
CPC分类号： H03L7/099 , H03B2200/0092 , H03L7/093 , H03L7/1976 , H03L2207/05
摘要： A device may include an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit may include a frequency control input to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.
摘要翻译： 设备可以包括振荡器电路，控制电路，频率检测器电路和处理器电路。 振荡器电路可以包括用于输出振荡器信号的频率控制输入。 振荡器信号的频率取决于施加到频率控制输入的输入信号。 控制电路被配置为向频率控制输入施加第一输入信号值，第二输入信号值和第三输入信号值。 频率检测器电路被配置为当第一输入信号值被施加到频率控制输入时检测振荡器信号的第一频率值，当第二输入信号值被施加到频率控制时，振荡器信号的第二频率值 输入和第三频率值，当第三输入信号值被施加到频率控制输入时。
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9.发明授权公开(公告)号：US07573347B2
公开(公告)日：2009-08-11
申请号：US11401393
申请日：2006-04-10
IPC分类号： H03B5/12
CPC分类号： H03L7/093 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03L7/099 , H03L7/18 , H03L2207/06
摘要： A digitally controlled oscillator device includes a programming input, a selection input and an oscillator core with a first capacitive element which is frequency determining and programmable. The first capacitive element is coupled to the programming input that receives a first data word by which an oscillating frequency of the oscillator device is programmed with a predetermined frequency step size. The oscillator device further includes a selection unit for selecting a mode which is coupled to the selection input that receives a mode selection signal. The mode is selectable from a plurality of modes depending on the mode selection signal and each mode from the plurality of modes is characterized by a predetermined frequency step size. The digitally controlled oscillator device also includes a deattenuation amplifier.
摘要翻译： 数字控制振荡器装置包括编程输入，选择输入和具有频率确定和可编程的第一电容元件的振荡器芯。 第一电容元件耦合到接收第一数据字的编程输入，通过该第一数据字，振荡器器件的振荡频率以预定频率步长编程。 振荡器装置还包括选择单元，用于选择耦合到接收模式选择信号的选择输入的模式。 该模式可以根据模式选择信号从多个模式中选择，并且来自多个模式的每个模式的特征在于预定的频率步长。 数字控制振荡器装置还包括去衰减放大器。
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公开(公告)号：US07304519B2
公开(公告)日：2007-12-04
申请号：US11293381
申请日：2005-12-02
申请人： Volker Neubauer
发明人： Volker Neubauer
IPC分类号： H03K21/00
CPC分类号： H03K3/012 , H03K3/00 , H03K3/35625 , H03K17/00
摘要： A data latch contains a supply connection, a reference ground potential connection and a data input. The input side of an inverter is connected to the data input, and it is coupled via a first switching device to the supply connection, and via a second switching device to the reference ground potential connection. Furthermore, a first multivibrator circuit having transistors of a first conductance type is provided, and is coupled to the supply connection. A second multivibrator circuit having transistors of a second conductance type is coupled to the reference ground potential connection. The transistors in the first and second multivibrator circuits in the data latch are connected to one another on the output side at a first node and at a second node, with the first node being connected to one output of the inverter, and the second node forming an output tap.
摘要翻译： 数据锁存器包含供电连接，参考地电位连接和数据输入。 逆变器的输入端连接到数据输入端，并通过第一开关器件耦合到电源连接，并通过第二开关器件耦合到参考地电位连接。 此外，提供具有第一电导型晶体管的第一多谐振荡器电路，并且耦合到电源连接。 具有第二电导型晶体管的第二多谐振荡器电路耦合到参考地电位连接。 数据锁存器中的第一和第二多谐振荡器电路中的晶体管在第一节点和第二节点处的输出侧彼此连接，第一节点连接到逆变器的一个输出端，第二节点形成 输出水龙头。
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