公开(公告)号：US07642158B2

公开(公告)日：2010-01-05

申请号：US11241878

申请日：2005-09-30

申请人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

发明人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

摘要翻译： 位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。 横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。 在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。 在阻塞区域之间，字线正常布置在位线上。

公开(公告)号：US20070075381A1

公开(公告)日：2007-04-05

申请号：US11241878

申请日：2005-09-30

申请人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

发明人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

摘要翻译： 位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。 横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。 在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。 在阻塞区域之间，字线正常布置在位线上。

公开(公告)号：US20070048951A1

公开(公告)日：2007-03-01

申请号：US11216526

申请日：2005-08-31

申请人： Hocine Boubekeur ,  Dominik Olligs ,  Torsten Mueller ,  Christoph Kleint ,  David Pritchard

发明人： Hocine Boubekeur ,  Dominik Olligs ,  Torsten Mueller ,  Christoph Kleint ,  David Pritchard

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： Dielectric gratings are formed between the word line stacks. Spacers are applied to the sidewalls of the word line stacks and the dielectric gratings. In the openings between the spacers, silicon is epitaxially grown on the upper surfaces of source/drain regions, which are implanted self-aligned to the word line stacks. A silicide is formed on the grown silicon, and a metal layer is applied and structured to form local interconnects, which connect the source/drain regions to upper bit lines.

摘要翻译： 介质光栅形成在字线堆叠之间。 间隔件被施加到字线堆叠和介质光栅的侧壁。 在间隔物之间​​的开口中，硅在源/漏区的上表面上外延生长，其被注入自对准到字线堆叠。 在生长的硅上形成硅化物，并且施加和构造金属层以形成局部互连，其将源极/漏极区域连接到高位线。

公开(公告)号：US20070001305A1

公开(公告)日：2007-01-04

申请号：US11172366

申请日：2005-06-30

申请人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

发明人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11568

摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.

摘要翻译： 半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。 在其中设置有具有接触孔的第二介质层。 接触孔在第一横向具有宽度。 该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。 导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。 导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

公开(公告)号：US07521351B2

公开(公告)日：2009-04-21

申请号：US11172366

申请日：2005-06-30

申请人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

发明人： Thomas Mikolajick ,  Torsten Mueller ,  Nicolas Nagel ,  Lars Bach ,  Dominik Olligs ,  Veronika Polei

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11568

摘要： A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional “contact to interconnect” structures.

摘要翻译： 半导体产品包括具有第一电介质层的衬底，该第一电介质层具有用于接触衬底中的有源区的接触孔填充物。 在其中设置有具有接触孔的第二介质层。 接触孔在第一横向具有宽度。 该产品还包括导线，每个导线穿过第二介电层中的接触孔，并接触第一介电层中的多个接触孔填充物。 导电线在第一横向方向上的宽度小于第二介电层的接触孔的宽度。 导线与接触孔填充物直接机械接触，从而消除了提供任何传统的“接触互连”结构的需要。

公开(公告)号：US20070077748A1

公开(公告)日：2007-04-05

申请号：US11241877

申请日：2005-09-30

申请人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

发明人： Dominik Olligs ,  Hocine Boubekeur ,  Veronika Polei ,  Nicolas Nagel ,  Torsten Mueller ,  Lars Bach ,  Thomas Mikolajick ,  Joachim Deppe

IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L27/115 ,  H01L21/76838 ,  H01L27/11521 ,  H01L27/11568

摘要： A semiconductor product (1) includes a plurality of wordlines extending along a first lateral direction (x) along a substrate surface (22) and also includes contact structures (3) as well as filling structures (4) therebetween. Along the first direction (x) the contact structures (3) and the filling structures (4) are arranged in alternating order between two respective wordlines. Each contact structure (3) serves to connect two active areas (23) separated by one respective trench isolation filling (24) to a respective bitline (14). Accordingly, the width of the first contact structures (3) is much larger than the width of the bitlines (14) along the first direction (x). According to embodiments of the invention, tapered upper portions (9) of the contact structures (3) are shaped, the upper portions (9) having a width being significantly smaller than the width of the contact structures (3) along the first direction (x). Thereby, forming the bitlines (14) in direct contact to top surfaces (7) of contact structures (3) is possible without the risk of short circuits between adjacent bitlines (14).

摘要翻译： 半导体产品（1）包括沿衬底表面（22）沿着第一横向（x）延伸的多个字线，并且还包括接触结构（3）以及它们之间的填充结构（4）。 沿着第一方向（x），接触结构（3）和填充结构（4）以两个相应字线之间的交替顺序排列。 每个接触结构（3）用于将由一个相应的沟槽隔离填充物（24）分开的两个有效区域（23）连接到相应的位线（14）。 因此，第一接触结构（3）的宽度比沿着第一方向（x）的位线（14）的宽度大得多。 根据本发明的实施例，接触结构（3）的锥形上部（9）成形，上部（9）的宽度明显小于接触结构（3）沿着第一方向（3）的宽度 X）。 因此，形成与接触结构（3）的顶表面（7）直接接触的位线（14）是可能的，而不会在相邻位线（14）之间发生短路。

公开(公告)号：US07935608B2

公开(公告)日：2011-05-03

申请号：US12131794

申请日：2008-06-02

申请人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

发明人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

IPC分类号： H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

摘要翻译： 提供了一种用于制造包括至少一个存储单元的集成电路的方法。 该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层 分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出 从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。

公开(公告)号：US20090294825A1

公开(公告)日：2009-12-03

申请号：US12131794

申请日：2008-06-02

申请人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

发明人： Frank Heinrichsdorff ,  Nicolas Nagel ,  Jens-Uwe Sachse ,  Andreas Voerckel ,  Dominik Olligs ,  Torsten Mueller

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/7881

摘要： A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means.

摘要翻译： 提供了一种用于制造包括至少一个存储单元的集成电路的方法。 该方法包括提供具有第一和第二侧面以及多个平行沟槽的衬底，使得在相邻沟槽之间形成分隔壁，用绝缘化合物填充沟槽，从而提供第一和第二侧面的第一绝缘层 分隔壁的上表面，其中第一侧布置在基板的第一侧上，提供具有第一和第二侧的第一导电层，其中第一侧布置在绝缘层的第二侧上，其中导电层突出 从基板表面提供具有第一和第二侧面的第二导电层，其中第一侧位于第一导电层的第二侧上，并通过各向异性蚀刻装置去除第二导电层的部分。

公开(公告)号：US20070082446A1

公开(公告)日：2007-04-12

申请号：US11246908

申请日：2005-10-07

申请人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

发明人： Dominik Olligs ,  Thomas Mikolajick ,  Josef Willer ,  Karl-Heinz Kuesters ,  Torsten Mueller

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/115 ,  H01L21/76897 ,  H01L27/11568

摘要： A method is provided for fabricating stacked non-volatile memory cells. A semiconductor wafer is provided having a plurality of diffusion regions forming buried bit lines. A charge-trapping layer and a conductive layer are deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed wherein an insulating layer is formed. An etch stop layer is deposited on the surface of the semiconductor wafer. Above the etch stop layer, a dielectric layer is deposited and is patterned so as to form contact holes. Subsequently, the contact holes are enlarged through the etch stop layer and the insulating layer to the buried bit lines.

摘要翻译： 提供了用于制造堆叠的非易失性存储单元的方法。 提供具有形成埋入位线的多个扩散区域的半导体晶片。 电荷捕获层和导电层沉积在半导体晶片的表面上。 在导电层的顶部使用掩模层，形成绝缘层的接触孔。 蚀刻停止层沉积在半导体晶片的表面上。 在蚀刻停止层上方，沉积介电层并图案化以形成接触孔。 随后，接触孔通过蚀刻停止层和绝缘层扩大到埋入位线。

公开(公告)号：US07368350B2

公开(公告)日：2008-05-06

申请号：US11313247

申请日：2005-12-20

申请人： Dominik Olligs ,  Torsten Mueller ,  Karl-Heinz Kuesters ,  Veronika Polei ,  Thomas Mikolajick ,  Josef Willer

发明人： Dominik Olligs ,  Torsten Mueller ,  Karl-Heinz Kuesters ,  Veronika Polei ,  Thomas Mikolajick ,  Josef Willer

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/76831 ,  H01L21/76888 ,  H01L21/76897 ,  H01L27/11568

摘要： A method for fabricating stacked non-volatile memory cells and non-volatile memory cell arrays are disclosed. A semiconductor wafer is provided having a charge-trapping layer and a conductive layer deposited on the surface of the semiconductor wafer. Using a mask layer on top of the conductive layer, contact holes are formed into which a contact fill material is deposited. A further conductive layer is deposited on the surface of the semiconductor wafer and is patterned so as to form word lines. The contact fill material is connected to a contact plug using the contact holes with the contact fill material as a landing pad.

摘要翻译： 公开了一种用于制造堆叠的非易失性存储单元和非易失性存储单元阵列的方法。 提供半导体晶片，其具有沉积在半导体晶片的表面上的电荷捕获层和导电层。 在导电层的顶部使用掩模层，形成接触填充材料沉积到其中的接触孔。 另外的导电层沉积在半导体晶片的表面上并被图案化以形成字线。 接触填充材料使用接触孔与接触填充材料作为着陆垫连接到接触塞。