公开(公告)号：US07867912B2

公开(公告)日：2011-01-11

申请号：US11676635

申请日：2007-02-20

申请人： Dirk Caspary ,  Arnd Scholz ,  Stefano Parascandola ,  Christoph Nölscher

发明人： Dirk Caspary ,  Arnd Scholz ,  Stefano Parascandola ,  Christoph Nölscher

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3086 ,  H01L21/3088 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/115

摘要： A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.

摘要翻译： 公开了制造半导体结构的方法。 在一个实施例中，在衬底上方提供第一掩模。 第一掩模包括沿着第一轴线延伸的第一掩模线。 在第一掩模上方提供第二掩模。 第二掩模包括沿着与第一轴相交的第二轴延伸的第二掩模线。 第一和第二掩模中的至少一个由音调分段方法形成。 可以在衬底中形成结构，其中第一和第二掩模作为组合掩模是有效的。 结构可以在重复线结构的最小光刻特征尺寸的范围内以间距等间隔。

公开(公告)号：US20070221979A1

公开(公告)日：2007-09-27

申请号：US11386456

申请日：2006-03-22

申请人： Dirk Caspary ,  Stefano Parascandola ,  Stephan Riedel

发明人： Dirk Caspary ,  Stefano Parascandola ,  Stephan Riedel

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： At least one memory layer is provided on a substrate surface. A plurality of parallel conductor strips is formed from electrically conductive material above the memory layer. Sidewalls of the conductor strips are provided with spacers of an electrically conductive material.

摘要翻译： 至少一个存储层设置在衬底表面上。 多个平行导体条由存储层上方的导电材料形成。 导体条的侧壁设置有导电材料的间隔物。

公开(公告)号：US07427548B2

公开(公告)日：2008-09-23

申请号：US11170187

申请日：2005-06-29

申请人： Stephan Riedel ,  Stefano Parascandola

发明人： Stephan Riedel ,  Stefano Parascandola

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L29/66833

摘要： A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling (7) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks (8) are formed.

摘要翻译： 在硅衬底（1）的主表面上施加包括下约束层（2），电荷俘获层（3）和上限制层（4）的存储层序列。 通过光刻步骤，蚀刻彼此间隔一定距离的平行沟槽，以界定有效面积。 沟槽填充（7）通过介电材料的生长或沉积或通过基底材料的选择性氧化来施加。 在去除外围区域中的电荷捕获层序列并且为寻址电路的晶体管提供的栅极电介质材料的沉积形成字线叠层（8）之后。

公开(公告)号：US20080197394A1

公开(公告)日：2008-08-21

申请号：US11676635

申请日：2007-02-20

申请人： Dirk Caspary ,  Arnd Scholz ,  Stefano Parascandola ,  Christoph Noelscher

发明人： Dirk Caspary ,  Arnd Scholz ,  Stefano Parascandola ,  Christoph Noelscher

IPC分类号： H01L29/94 ,  G03F1/00 ,  H01L21/311 ,  H01L27/108

CPC分类号： H01L21/3086 ,  H01L21/3088 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/115

摘要： A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.

摘要翻译： 公开了制造半导体结构的方法。 在一个实施例中，在衬底上方提供第一掩模。 第一掩模包括沿着第一轴线延伸的第一掩模线。 在第一掩模上方提供第二掩模。 第二掩模包括沿着与第一轴相交的第二轴延伸的第二掩模线。 第一和第二掩模中的至少一个由音调分段方法形成。 可以在衬底中形成结构，其中第一和第二掩模作为组合掩模是有效的。 结构可以在重复线结构的最小光刻特征尺寸的范围内以间距等间隔。

公开(公告)号：US20070026684A1

公开(公告)日：2007-02-01

申请号：US11194489

申请日：2005-08-01

申请人： Stefano Parascandola ,  Dirk Caspary

发明人： Stefano Parascandola ,  Dirk Caspary

IPC分类号： H01L21/311 ,  H01L21/461 ,  B44C1/22

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： Spacers are formed on sidewalls of striplike parts of a pattern layer of periodic structure. The pattern layer is removed, and the spacers are covered with a further spacer layer, which is then structured to second sidewall spacers. Gaps between the spacers are filled with a complementary layer. The upper surface is planarized to a lower surface level, leaving a periodic succession of the first spacers, the second spacers and the residual parts of the complementary layer. The lateral dimensions are adapted in such a manner that a removal of one or two of the remaining layers renders a periodic pattern of smaller pitch.

摘要翻译： 间隔物形成在周期性结构的图案层的带状部分的侧壁上。 去除图案层，并且间隔物被另外的间隔层覆盖，然后隔离层被构造成第二侧壁间隔物。 间隔物之间​​的间隙填充有互补层。 上表面被平坦化到较低的表面水平，留下第一间隔物，第二间隔物和互补层的残留部分的周期性连续。 横向尺寸以这样一种方式进行调整，使得一个或两个剩余的层的移除呈现较小间距的周期性图案。

公开(公告)号：US07642158B2

公开(公告)日：2010-01-05

申请号：US11241878

申请日：2005-09-30

申请人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

发明人： Stefano Parascandola ,  Roman Knoefler ,  Stephan Riedel ,  Dominik Olligs ,  Torsten Mueller ,  Dirk Caspary

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11565 ,  H01L27/11568

摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.

摘要翻译： 位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。 横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。 在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。 在阻塞区域之间，字线正常布置在位线上。

公开(公告)号：US20070212892A1

公开(公告)日：2007-09-13

申请号：US11588429

申请日：2006-10-27

申请人： Dirk Caspary ,  Stefano Parascandola

发明人： Dirk Caspary ,  Stefano Parascandola

IPC分类号： H01L21/302

CPC分类号： H01L21/0337 ,  H01L21/0338

摘要： A first hardmask layer is provided over a substrate, and a second hardmask layer is provided over the first hardmask layer. The second hardmask layer is patterned to form a second hardmask structure having sidewalls. A sacrificial layer of a sacrificial material is conformally deposited such that the deposited sacrificial layer has substantially horizontal and vertical portions. The horizontal portions of the sacrificial layer are removed to form lines of the sacrificial material adjacent to the sidewalls of the second hardmask lines. The sacrificial layer is at least partially removed to structure the sacrificial material and the remaining sacrificial layer is used to structure the first hardmask. The second hardmask structures is removed to uncover portions of the first hardmask. Uncovered portions of the substrate are etched, thereby forming structures in the substrate below the first hardmask.

摘要翻译： 在衬底上提供第一硬掩模层，并且在第一硬掩模层上提供第二硬掩模层。 图案化第二硬掩模层以形成具有侧壁的第二硬掩模结构。 牺牲材料的牺牲层被共形沉积，使得沉积的牺牲层具有基本水平和垂直的部分。 去除牺牲层的水平部分以形成与第二硬掩模线的侧壁相邻的牺牲材料的线。 至少部分去除牺牲层以构造牺牲材料，并且使用剩余的牺牲层来构造第一硬掩模。 移除第二硬掩模结构以露出​​第一硬掩模的部分。 对衬底的未覆盖部分进行蚀刻，从而在第一硬掩模下面的衬底中形成结构。

公开(公告)号：US20070045717A1

公开(公告)日：2007-03-01

申请号：US11216525

申请日：2005-08-31

申请人： Stefano Parascandola ,  Stephan Riedel

发明人： Stefano Parascandola ,  Stephan Riedel

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/1203

摘要： A plurality of parallel shallow trenches is etched at a main surface of a semiconductor substrate. A sequence of dielectric materials that are suitable for charge-trapping is applied on the whole surface including sidewalls and bottom surfaces of the etched trenches. This layer sequence completely fills the trenches and forms the shallow trench isolations. An additional layer can be provided between the memory layer and the top layer in order to achieve a planar upper surface.

摘要翻译： 在半导体衬底的主表面上蚀刻多个平行的浅沟槽。 适用于电荷捕获的介电材料的序列被施加在包括蚀刻沟槽的侧壁和底表面的整个表面上。 该层序列完全填充沟槽并形成浅沟槽隔离。 可以在存储层和顶层之间提供附加层，以实现平坦的上表面。

公开(公告)号：US07378727B2

公开(公告)日：2008-05-27

申请号：US11327054

申请日：2006-01-06

申请人： Dirk Caspary ,  Stefano Parascandola

发明人： Dirk Caspary ,  Stefano Parascandola

IPC分类号： H01L23/48

CPC分类号： H01L27/10 ,  H01L27/105 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory device includes a semiconductor substrate having a surface, a plurality of first and second conductive lines, a plurality of memory cells, and a plurality of landing pads. Each of the first conductive lines has a line width wb and two neighboring ones of the first conductive lines having a distance bs from each other. Each of the second conductive lines has a line width wl and two neighboring ones of the second conductive lines having a distance ws from each other. Each memory cell is accessible by addressing corresponding ones of said first and second conductive lines. Each of the landing pads are made of a conductive material and are connected with a corresponding one of said second conductive lines. Each of said landing pads has a width wp and length lp and the line width wl of each of the second conductive lines is larger than the distance ws and the width wp of each of the landing pads is larger than the line width wl and the length lp of each of the landing pads is larger than the line width wl.

摘要翻译： 存储器件包括具有表面，多个第一和第二导电线，多个存储单元和多个着陆焊盘的半导体衬底。 每个第一导线具有线宽度wb和彼此之间具有距离bs的第一导线中的两个相邻的导线。 每个第二导线具有线宽w1和彼此之间具有距离ws的两条相邻的第二导线。 通过寻址所述第一和第二导线中相应的一个可访问每个存储单元。 每个着陆焊盘由导电材料制成并且与相应的所述第二导电线连接。 每个所述着陆焊盘具有宽度wp和长度lp，并且每个第二导线的线宽w1大于距离ws，并且每个着陆焊盘的宽度wp大于线宽w1和长度 每个着陆垫的lp大于线宽w1。

公开(公告)号：US07291560B2

公开(公告)日：2007-11-06

申请号：US11194489

申请日：2005-08-01

申请人： Stefano Parascandola ,  Dirk Caspary

发明人： Stefano Parascandola ,  Dirk Caspary

IPC分类号： H01L21/70

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： Spacers are formed on sidewalls of striplike parts of a pattern layer of periodic structure. The pattern layer is removed, and the spacers are covered with a further spacer layer, which is then structured to second sidewall spacers. Gaps between the spacers are filled with a complementary layer. The upper surface is planarized to a lower surface level, leaving a periodic succession of the first spacers, the second spacers and the residual parts of the complementary layer. The lateral dimensions are adapted in such a manner that a removal of one or two of the remaining layers renders a periodic pattern of smaller pitch.

摘要翻译： 间隔物形成在周期性结构的图案层的带状部分的侧壁上。 去除图案层，并且间隔物被另外的间隔层覆盖，然后隔离层被构造成第二侧壁间隔物。 间隔物之间​​的间隙填充有互补层。 上表面被平坦化到较低的表面水平，留下第一间隔物，第二间隔物和互补层的残留部分的周期性连续。 横向尺寸以这样一种方式进行调整，使得一个或两个剩余的层的移除呈现较小间距的周期性图案。