公开(公告)号：US20100211336A1

公开(公告)日：2010-08-19

申请号：US12388593

申请日：2009-02-19

申请人： Philip E. Madrid ,  Stephen C. Ennis

发明人： Philip E. Madrid ,  Stephen C. Ennis

IPC分类号： G06F19/00 ,  G01K1/00

CPC分类号： H01L25/065 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

摘要： Information of a first type is determined at an integrated circuit die of a data processing device included an integrated circuit package. The integrated circuit package includes the first integrated circuit die and a second integrated circuit die. Information of a second type is determined at the integrated circuit die. The first and second type of information is transmitted from the integrated circuit die to another integrated circuit die using a time-divided multiplexed protocol by transmitting the first information during a first time slot of the protocol and transmitting the second information during a second time slot of the protocol.

摘要翻译： 在包括集成电路封装的数据处理装置的集成电路管芯处确定第一类型的信息。 集成电路封装包括第一集成电路管芯和第二集成电路管芯。 在集成电路管芯处确定第二类型的信息。 第一和第二类型的信息通过在协议的第一时隙期间发送第一信息并使用时分复用协议从集成电路管芯传输到另一个集成电路管芯，并在第二时隙期间发送第二信息 协议。

公开(公告)号：US07840780B2

公开(公告)日：2010-11-23

申请号：US12098303

申请日：2008-04-04

申请人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

发明人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

IPC分类号： G06F9/00

CPC分类号： G06F15/8007

摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

公开(公告)号：US20080184009A1

公开(公告)日：2008-07-31

申请号：US12098303

申请日：2008-04-04

申请人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

发明人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F15/8007

摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

公开(公告)号：US06820151B2

公开(公告)日：2004-11-16

申请号：US09978379

申请日：2001-10-15

申请人： Stephen C. Ennis

发明人： Stephen C. Ennis

IPC分类号： G06F1314

CPC分类号： H04L47/6285 ,  H04L47/50

摘要： A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.

摘要翻译： 用于计算机系统的输入/输出节点的饥饿避免机制。 调度器单元包括第一缓冲电路和第二缓冲电路。 第一缓冲电路包括用于存储从第一源接收的所选控制命令的第一多个缓冲器，并且第二缓冲电路包括用于存储从第二源接收的所选控制命令的第二多个缓冲器。 调度器还包括耦合到第一缓冲电路和第二缓冲电路的仲裁电路。 仲裁电路可以被配置为在存储在第一缓冲器电路中的控制命令和存储在第二缓冲器电路中的控制命令之间进行仲裁。 选择的仲裁周期的结果可以取决于由于不可用目的地而阻止来自缓冲器中的给定缓冲器的控制命令的次数。

公开(公告)号：US06681274B2

公开(公告)日：2004-01-20

申请号：US09978378

申请日：2001-10-15

申请人： Stephen C. Ennis

发明人： Stephen C. Ennis

IPC分类号： G06F1300

CPC分类号： G06F13/387 ,  G06F13/4036

摘要： A virtual channel buffer bypass in a computer system input/output node. A control unit of an input/output node for a computer system includes a buffer circuit configured to receive control commands. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. The buffer circuit may also be configured to determine whether each of the plurality of buffers is empty prior to storing a particular control command corresponding to a given one of the plurality of buffers. In addition, the buffer circuit may be configured to cause the particular control command to bypass the given one of the plurality of buffers in response to determining that each of the plurality of buffers is empty.

摘要翻译： 计算机系统输入/输出节点中的虚拟通道缓冲区旁路。 用于计算机系统的输入/输出节点的控制单元包括被配置为接收控制命令的缓冲电路。 缓冲电路可以包括多个缓冲器，每个缓冲器对应于多个虚拟通道的相应虚拟通道，用于存储属于相应虚拟通道的所选择的控制命令。 缓冲电路还可以被配置为在存储对应于多个缓冲器中的给定缓冲器的特定控制命令之前，确定多个缓冲器中的每一个是否为空。 此外，缓冲器电路可以被配置为响应于确定多个缓冲器中的每一个是空的，使特定的控制命令绕过多个缓冲器中的给定的一个缓冲器。

公开(公告)号：US06571332B1

公开(公告)日：2003-05-27

申请号：US09546979

申请日：2000-04-11

申请人： Paul C. Miranda ,  Larry D. Hewitt ,  Stephen C. Ennis

发明人： Paul C. Miranda ,  Larry D. Hewitt ,  Stephen C. Ennis

IPC分类号： G06F926

CPC分类号： G06F13/1631

摘要： A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is configured to generate a second tag using the size of said first memory request added to the first tag. The first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request. The second generator circuit may be further configured to generate a third tag using the size of the second memory request added to said second tag.

摘要翻译： 一种用于组合事务重新排序和缓冲管理的方法和装置。 该装置可以包括缓冲器，第一发生器电路和第二发生器电路。 缓冲器被配置为存储在多个可寻址位置中从存储器控制器接收的存储器事务响应。 第一发生器电路被配置为响应于接收到第一存储器请求而产生用与缓冲器中的地址相对应的第一标签编码的第一存储器事务请求。 第二发生器电路被配置为使用添加到第一标签的所述第一存储器请求的大小来生成第二标签。 第一生成器电路可以被配置为响应于接收到与第一存储器请求连续的第二存储器请求，来生成与缓冲器中的第二地址对应的第二标签编码的第二存储器事务请求。 第二发生器电路还可以被配置为使用添加到所述第二标签的第二存储器请求的大小来生成第三标签。

公开(公告)号：US20120096288A1

公开(公告)日：2012-04-19

申请号：US12903888

申请日：2010-10-13

申请人： Benjamin D. Bates ,  Brian E. Williams ,  Stephen C. Ennis

发明人： Benjamin D. Bates ,  Brian E. Williams ,  Stephen C. Ennis

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/206 ,  G06F1/3206 ,  G06F1/325 ,  G06F1/3287 ,  Y02D10/16 ,  Y02D10/171

摘要： Techniques are disclosed relating to controlling power consumption of temperature sensors in integrated circuits. In one embodiment, an integrated circuit is disclosed that includes a temperature sensor that is configured to determine a temperature of the integrated circuit. The integrated circuit also includes a sensor controller that is configured to vary power consumption of the temperature sensor based, at least in part, on the determined temperature. In some embodiments, the integrated circuit may determine a sampling rate of the temperature sensor based, at least in part, on the determined temperature and a temperature threshold of the integrated circuit. The integrated circuit may then vary the power consumption of the temperature sensor by periodically disabling the temperature sensor based on the determined sampling rate. In some embodiments, the integrated circuit may also vary the power consumption of the temperature sensor based on the operating state of one or more processing cores in the integrated circuit.

摘要翻译： 公开了关于控制集成电路中的温度传感器的功率消耗的技术。 在一个实施例中，公开了一种集成电路，其包括被配置为确定集成电路的温度的温度传感器。 集成电路还包括传感器控制器，其被配置为至少部分地基于所确定的温度来改变温度传感器的功率消耗。 在一些实施例中，集成电路可以至少部分地基于所确定的温度和集成电路的温度阈值来确定温度传感器的采样率。 然后，集成电路可以基于所确定的采样速率周期性地禁用温度传感器来改变温度传感器的功耗。 在一些实施例中，集成电路还可以基于集成电路中的一个或多个处理核的操作状态改变温度传感器的功耗。

公开(公告)号：US07996653B2

公开(公告)日：2011-08-09

申请号：US12899979

申请日：2010-10-07

申请人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

发明人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

IPC分类号： G06F9/30

CPC分类号： G06F15/8007

摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

公开(公告)号：US07383423B1

公开(公告)日：2008-06-03

申请号：US10957250

申请日：2004-10-01

申请人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

发明人： William A. Hughes ,  Vydhyanathan Kalyanasundharam ,  Kiran K. Bondalapati ,  Philip E. Madrid ,  Stephen C. Ennis

IPC分类号： G06F15/00

CPC分类号： G06F15/8007

摘要： In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e.g. a chip multiprocessor).

摘要翻译： 在一个实施例中，节点包括多个处理器核心和节点控制器，其被配置为接收寻址第一寄存器的第一读取操作。 节点控制器被配置为响应于第一读取操作而返回第一值，取决于哪个处理器核发送第一读取操作。 在另一个实施例中，节点包括处理器核心和节点控制器。 节点控制器包括由处理器核共享的队列。 处理器核被配置为以每N个时钟周期一个最大速率发送通信，其中N是等于处理器核心数的整数。 在另一个实施例中，节点包括处理器核和由处理器核共享的多个保险丝。 在一些实施例中，节点组件被集成到单个集成电路芯片（例如，芯片多处理器）上。

公开(公告)号：US06807599B2

公开(公告)日：2004-10-19

申请号：US09978349

申请日：2001-10-15

申请人： Stephen C. Ennis ,  Larry D. Hewitt

发明人： Stephen C. Ennis ,  Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/128

摘要： A computer system I/O node. An input/output node for a computer system includes a first receiver unit configured to receive a first command on a first communication path and a first transmitter unit coupled to transmit a first corresponding command that corresponds to the first command on a second communication path. The input/output node also includes a second receiver unit configured to receive a second command on a third communication path and a second transmitter unit coupled to transmit a second corresponding command that corresponds to the second command on a fourth communication path. Further, the input/output node includes a bridge unit coupled to receive selected commands from the first receiver and the second receiver and configured to transmit commands corresponding to the selected commands upon a peripheral bus.

摘要翻译： 计算机系统I / O节点。 用于计算机系统的输入/输出节点包括被配置为在第一通信路径上接收第一命令的第一接收器单元和耦合以在第二通信路径上发送对应于第一命令的第一对应命令的第一发送器单元。 输入/输出节点还包括被配置为在第三通信路径上接收第二命令的第二接收器单元和耦合以在第四通信路径上发送对应于第二命令的第二对应命令的第二发送器单元。 此外，输入/输出节点包括耦合以从第一接收器和第二接收器接收所选命令的桥单元，并且被配置为在外围总线上发送与所选命令相对应的命令。