公开(公告)号：US5949737A

公开(公告)日：1999-09-07

申请号：US116767

申请日：1998-07-16

申请人： Stephen L. Casper ,  Ward Parkinson

发明人： Stephen L. Casper ,  Ward Parkinson

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1015 ,  G11C8/18

摘要： A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition. Alternatively, the memory device may include a row decoder that is coupled between the latch and the array, and enables a row of memory cells identified by the row address. A control circuit is coupled to the array, receives the row address strobe, and enables the array to output additional data from the identified row even when the row address strobe is at the inactive level. Furthermore, the memory device may include both the control circuit and the row decoder that allows the row address to propagate therethrough while the row address strobe is at an inactive level.

摘要翻译： 存储器件包括以行和列布置的存储单元阵列。 行地址解码器允许行地址传播通过，而行地址选通处于非活动逻辑电平。 响应于行地址选通从无效电平转换到有效电平，解码器使能由行地址选择的一行存储器单元。 行地址锁存器响应于行地址选通的转换存储行地址。 存储器件还可以包括转换检测器，其监视行转换的行地址。 延迟电路耦合到解码器，锁存器和检测器。 如果监视器检测到行地址的转变，则延迟电路在这种转换之后的至少预定时间延迟了存储器单元的行的使能和行地址的存储。 或者，存储器件可以包括耦合在锁存器和阵列之间的行解码器，并且使能由行地址识别的一行存储器单元。 控制电路耦合到阵列，接收行地址选通，并且使得阵列能够从所识别的行输出附加数据，即使当行地址选通处于非活动电平时。 此外，存储器件可以包括允许行地址传播通过其中行地址选通处于非活动级的控制电路和行解码器。

公开(公告)号：US5715208A

公开(公告)日：1998-02-03

申请号：US536005

申请日：1995-09-29

申请人： Stephen L. Casper ,  Ward Parkinson

发明人： Stephen L. Casper ,  Ward Parkinson

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1015 ,  G11C8/18

摘要： A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition. Alternatively, the memory device may include a row decoder that is coupled between the latch and the array, and enables a row of memory cells identified by the row address. A control circuit is coupled to the array, receives the row address strobe, and enables the array to output additional data from the identified row even when the row address strobe is at the inactive level. Furthermore, the memory device may include both the control circuit and the row decoder that allows the row address to propagate therethrough while the row address strobe is at an inactive level.

公开(公告)号：US5831927A

公开(公告)日：1998-11-03

申请号：US848340

申请日：1997-04-30

申请人： Stephen L. Casper ,  Ward Parkinson

发明人： Stephen L. Casper ,  Ward Parkinson

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1015 ,  G11C8/18

摘要： A memory device includes an array of memory cells arranged in rows and columns. A row-address decoder allows a row address to propagate therethrough while a row address strobe is at an inactive logic level. In response to a transition of the row address strobe from the inactive level to an active level, the decoder enables a row of memory cells selected by the row address. A row-address latch stores the row address in response to the transition of the row address strobe. The memory device may also include a transition detector that monitors the row address for a transition thereof. A delay circuit is coupled to the decoder, the latch, and the detector. If the monitor detects a transition of the row address, the delay circuit delays the enabling of the row of memory cells and the storing of the row address at least predetermined time after such a transition. Alternatively, the memory device may include a row decoder that is coupled between the latch and the array, and enables a row of memory cells identified by the row address. A control circuit is coupled to the array, receives the row address strobe, and enables the array to output additional data from the identified row even when the row address strobe is at the inactive level. Furthermore, the memory device may include both the control circuit and the row decoder that allows the row address to propagate therethrough while the row address strobe is at an inactive level.

公开(公告)号：US07995415B2

公开(公告)日：2011-08-09

申请号：US12082579

申请日：2008-04-11

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1006 ,  G11C7/1078 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4096 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.

摘要翻译： 动态随机存取存储器（“DRAM”）设备可以在正常刷新模式或静态刷新模式（诸如自刷新模式）中操作。 电池板电压选择器将正常刷新模式下的电源电压的一半电压与DRAM阵列的单元板耦合，并且当刷新存储器单元时，静态刷新模式。 在静态刷新模式下的刷新突发之间，单元板电压选择器将降低的电压耦合到单元板。 这降低了形成在各个存取晶体管的源极/漏极与衬底之间的二极管结上的电压。 降低的电压降低了从存储单元电容器流出的放电电流，从而允许减少所需的刷新率并因此降低功耗。

公开(公告)号：US06922368B2

公开(公告)日：2005-07-26

申请号：US10820406

申请日：2004-04-08

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： F01D5/30 ,  F01D9/04 ,  G11C7/20 ,  G11C11/4072 ,  G11C7/00

CPC分类号： G11C11/4072 ,  G11C7/20

摘要： A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

摘要翻译： 在初始施加电力时减少启用动态随机存取存储器（DRAM）的时间的方法和装置包括在初始上电时产生内部RAS信号以产生内部电压。 在短时间延迟结束后，内部RAS脉冲被置位。 在内部RAS脉冲被置位之后，数字线对上的电压用读出放大器放大。 然后，数字线对上的放大电压用平衡电路平衡。 平衡电压也通过平衡电路耦合以对存储单元电容器的公共板充电。

公开(公告)号：US06760264B2

公开(公告)日：2004-07-06

申请号：US10224950

申请日：2002-08-20

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C700

CPC分类号： G11C11/4072 ,  G11C7/20

摘要： A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

公开(公告)号：US06587978B1

公开(公告)日：2003-07-01

申请号：US08603943

申请日：1996-02-20

申请人： Todd A. Merritt ,  George B. Raad ,  Stephen L. Casper

发明人： Todd A. Merritt ,  George B. Raad ,  Stephen L. Casper

IPC分类号： G11C2900

CPC分类号： G11C29/50012 ,  G11C11/401 ,  G11C29/14

摘要： The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a pulse width of an internal control signal to stress the DRAM during a test mode.

摘要翻译： 本发明是具有在板上制造的电子测试键的动态随机存取存储器（DRAM）器件，并且是用于测试DRAM的方法。 电子测试键产生在测试模式期间影响内部控制信号的脉冲宽度变化以胁迫DRAM的信号。

公开(公告)号：US06475851B1

公开(公告)日：2002-11-05

申请号：US09124478

申请日：1998-07-29

申请人： Stephen L. Casper ,  Brian M. Shirley ,  Kevin G. Duesman

发明人： Stephen L. Casper ,  Brian M. Shirley ,  Kevin G. Duesman

IPC分类号： H01L218238

CPC分类号： H01L21/765 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/10805 ,  Y10T307/839

摘要： Adjacent unassociated field-effect transistors are formed from a single continuous layer of uniformly doped material in a semiconductor substrate. An insulating layer is formed over the active layer. A number of gates in a conductive layer define the transistors. Forming a connection between one of the gates and a reference potential forms a boundary between the unassociated transistors across the active material by preventing carrier transport thereacross.

摘要翻译： 相邻的非相关场效应晶体管由半导体衬底中的均匀掺杂材料的单个连续层形成。 在有源层上形成绝缘层。 导电层中的多个栅极限定晶体管。 在一个栅极和参考电位之间形成连接，通过防止跨越其的载流子传输，形成跨过活性材料的非相关晶体管之间的边界。

公开(公告)号：US06388314B1

公开(公告)日：2002-05-14

申请号：US08516171

申请日：1995-08-17

申请人： Stephen L. Casper ,  Timothy J. Allen ,  D. Mark Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

发明人： Stephen L. Casper ,  Timothy J. Allen ,  D. Mark Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

IPC分类号： H01L2352

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/1815 ,  H01L2924/00

摘要： A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

摘要翻译： 描述了16兆比特（224）或更大密度的单沉积层金属动态随机存取存储器（DRAM）部件，其允许适用于工业标准的300ml宽SOJ（小外形J翼）封装或TSOP （薄型，小外形封装），与以前的双金属沉积分层16兆位DRAM设计相比，速度损失很少或没有速度损失。 这是通过使用允许单个金属层信号路径的管芯架构来实现的，以及引线框架的新颖使用以去除芯片的大部分功率，从而允许较小的速度优化的DRAM。 使用单个沉积层金属导致较低的生产成本和较短的生产时间。

公开(公告)号：US6141270A

公开(公告)日：2000-10-31

申请号：US70520

申请日：1998-04-29

申请人： Stephen L. Casper

发明人： Stephen L. Casper

IPC分类号： G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4074 ,  G11C11/4091 ,  G11C7/06

摘要： A cell margin test method for a dynamic cell plate sensing (DCPS) memory array. In a DCPS memory array, voltage moves on both a digitline and a cell plate line associated with an accessed memory cell. Voltage movement on the digitline and its associated cell plate line is in opposite directions, ie., voltage on one line moves up (goes high) and voltage on the other line moves down (goes low). Because voltage movement is in opposite directions, this produces a voltage swing which is larger than that produced by a conventional digitline pair approach, in which one digitline remains at a reference potential and the other digitline moves away from the reference potential. A method is provided for a DCPS memory array which tests sense amplifier latching with a voltage swing produced with one line (either a digitline or a cell plate line) held at a reference potential and another line (either a digitline or a cell plate line) moved away from the reference potential.

摘要翻译： 用于动态细胞板感测（DCPS）存储器阵列的细胞边缘测试方法。 在DCPS存储器阵列中，电压在与所访问的存储器单元相关联的数字线和单元板线上移动。 数字线及其相关单元板线上的电压移动方向相反，即，一条线上的电压向上移动（变高），另一条线上的电压向下移动（变为低电平）。 因为电压移动是相反的方向，所以产生的电压摆幅大于常规数字线对方法产生的电压摆幅，其中一个数字线保持在参考电位，另一个数字线移动远离参考电位。 提供了一种用于DCPS存储器阵列的方法，其用保持在参考电位的一行（数字线或单元格板线）和另一行（数字线或单元格板线）产生的电压摆幅来测试读出放大器锁存， 远离参考潜力。