Single deposition layer metal dynamic random access memory
    1.
    发明授权
    Single deposition layer metal dynamic random access memory 失效
    单沉积层金属动态随机存取存储器

    公开(公告)号:US06388314B1

    公开(公告)日:2002-05-14

    申请号:US08516171

    申请日:1995-08-17

    IPC分类号: H01L2352

    摘要: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

    摘要翻译: 描述了16兆比特(224)或更大密度的单沉积层金属动态随机存取存储器(DRAM)部件,其允许适用于工业标准的300ml宽SOJ(小外形J翼)封装或TSOP (薄型,小外形封装),与以前的双金属沉积分层16兆位DRAM设计相比,速度损失很少或没有速度损失。 这是通过使用允许单个金属层信号路径的管芯架构来实现的,以及引线框架的新颖使用以去除芯片的大部分功率,从而允许较小的速度优化的DRAM。 使用单个沉积层金属导致较低的生产成本和较短的生产时间。

    Method of making a single-deposition-layer-metal dynamic random access memory
    3.
    发明授权
    Method of making a single-deposition-layer-metal dynamic random access memory 失效
    制备单沉积层金属动态随机存取存储器的方法

    公开(公告)号:US06569727B1

    公开(公告)日:2003-05-27

    申请号:US08852909

    申请日:1997-05-08

    IPC分类号: H01L218242

    摘要: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

    摘要翻译: 描述了16兆比特(224)或更大密度的单沉积层金属动态随机存取存储器(DRAM)部件,其允许适用于工业标准的300ml宽SOJ(小外形J翼)封装或TSOP (薄型,小外形封装),与以前的双金属沉积分层16兆位DRAM设计相比,速度损失很少或没有速度损失。 这是通过使用允许单个金属层信号路径的管芯架构来实现的,以及引线框架的新颖使用以去除芯片的大部分功率,从而允许较小的速度优化的DRAM。 使用单个沉积层金属导致较低的生产成本和较短的生产时间。

    Single deposition layer metal dynamic random access memory
    4.
    发明授权
    Single deposition layer metal dynamic random access memory 失效
    单沉积层金属动态随机存取存储器

    公开(公告)号:US06274928B1

    公开(公告)日:2001-08-14

    申请号:US08852911

    申请日:1997-05-08

    IPC分类号: H01L2352

    摘要: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

    摘要翻译: 描述了16兆比特(224)或更大密度的单沉积层金属动态随机存取存储器(DRAM)部件,其允许适用于工业标准的300ml宽SOJ(小外形J翼)封装或TSOP (薄型,小外形封装),与以前的双金属沉积分层16兆位DRAM设计相比,速度损失很少或没有速度损失。 这是通过使用允许单个金属层信号路径的管芯架构来实现的,以及引线框架的新颖使用以去除芯片的大部分功率,从而允许较小的速度优化的DRAM。 使用单个沉积层金属导致较低的生产成本和较短的生产时间。

    Circuit for providing isolation of integrated circuit active areas
    6.
    发明授权
    Circuit for providing isolation of integrated circuit active areas 失效
    用于提供集成电路有源区隔离的电路

    公开(公告)号:US06242782B1

    公开(公告)日:2001-06-05

    申请号:US09124283

    申请日:1998-07-29

    IPC分类号: H01L2994

    摘要: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

    摘要翻译: 连接在半导体衬底中形成的相邻晶体管的非相关有源区的隔离栅的提供不需要额外的工艺步骤来提供相邻晶体管的有效隔离。 隔离栅极连接到参考,以确保未形成非相关活动区域之间的通道,并提供有效的隔离。 相邻的晶体管被​​交叉耦合以形成用于动态随机存取存储器件的读出放大器。

    Circuit for providing isolation of integrated circuit active areas
    7.
    发明授权
    Circuit for providing isolation of integrated circuit active areas 失效
    提供集成电路有源区隔离的方法

    公开(公告)号:US06475851B1

    公开(公告)日:2002-11-05

    申请号:US09124478

    申请日:1998-07-29

    IPC分类号: H01L218238

    摘要: Adjacent unassociated field-effect transistors are formed from a single continuous layer of uniformly doped material in a semiconductor substrate. An insulating layer is formed over the active layer. A number of gates in a conductive layer define the transistors. Forming a connection between one of the gates and a reference potential forms a boundary between the unassociated transistors across the active material by preventing carrier transport thereacross.

    摘要翻译: 相邻的非相关场效应晶体管由半导体衬底中的均匀掺杂材料的单个连续层形成。 在有源层上形成绝缘层。 导电层中的多个栅极限定晶体管。 在一个栅极和参考电位之间形成连接,通过防止跨越其的载流子传输,形成跨过活性材料的非相关晶体管之间的边界。