公开(公告)号：US07350018B2

公开(公告)日：2008-03-25

申请号：US11595370

申请日：2006-11-08

申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

IPC分类号： G06F12/16

CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体中读取的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

公开(公告)号：US07292497B2

公开(公告)日：2007-11-06

申请号：US11379194

申请日：2006-04-18

申请人： Brian M. Shirley ,  David R. Brown

发明人： Brian M. Shirley ,  David R. Brown

IPC分类号： G11C8/00 ,  G11C5/02

CPC分类号： G11C7/1042 ,  G11C7/065 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another bank. Banks in different rows can be simultaneously accessed.

摘要翻译： 多行存储器件包括行和列的存储器核。 每行包括来自另一个存储体的存储器核心的来自一个存储体的存储器核心。 可以同时访问不同行中的行。

公开(公告)号：US06862654B1

公开(公告)日：2005-03-01

申请号：US09642546

申请日：2000-08-17

申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

IPC分类号： G11C7/10 ,  G11C11/406 ,  G11C11/409 ,  G11C15/04 ,  G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且还包括2个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

公开(公告)号：US06771553B2

公开(公告)日：2004-08-03

申请号：US10056935

申请日：2001-10-18

申请人： Timothy B. Cowles ,  Brian M. Shirley ,  Greg A. Blodgett

发明人： Timothy B. Cowles ,  Brian M. Shirley ,  Greg A. Blodgett

IPC分类号： G11C700

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4065 ,  G11C2211/4067

摘要： A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

摘要翻译： 在DRAM的自动刷新期间，省电电路禁用用于命令和地址信号的输入缓冲器。 输入缓冲区在自动刷新结束时以不会导致生成伪指令的方式重新启用。 只要禁止命令信号的输入缓冲器，省电电路就可以通过将内部命令信号偏置为“无操作”命令来防止伪指令。 DRAM也可以被置于在自动刷新结束时自动转换到低功率预充电模式的模式，以进一步降低由DRAM消耗的功率。

公开(公告)号：US06552945B2

公开(公告)日：2003-04-22

申请号：US09768897

申请日：2001-01-23

申请人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

发明人： Christopher B. Cooper ,  Ming-Bo Liu ,  Chris G. Martin ,  Troy A. Manning ,  Stephen L. Casper ,  Charles H. Dennison ,  Brian M. Shirley ,  Brian L. Brown ,  Shubneesh Batra

IPC分类号： G11C704

CPC分类号： G11C7/04 ,  G11C7/1045 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4078

摘要： A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

摘要翻译： 一种用于在集成电路中存储温度阈值的方法包括：测量集成电路的相对于温度的操作参数，计算集成电路性能超过预定规格的最大温度，并将积分电路性能中最大温度的参数存储在集成电路中的比较电路中 通过在比较电路中选择性地吹入可熔设备。 可熔断器件可以是反熔丝。 因此，集成电路能够向集成电路外部的设备提供信号，以指示集成电路可能太热而无法正常工作。

公开(公告)号：US06445636B1

公开(公告)日：2002-09-03

申请号：US09641881

申请日：2000-08-17

申请人： Brent Keeth ,  Brian M. Shirley ,  Kevin J. Ryan ,  Charles H. Dennison

发明人： Brent Keeth ,  Brian M. Shirley ,  Kevin J. Ryan ,  Charles H. Dennison

IPC分类号： G11C700

CPC分类号： G11C11/40618 ,  G11C7/1042 ,  G11C11/406

摘要： A method and system for refreshing a dynamic random access memory (“DRAM”) includes a pair of memory arrays for each of a plurality of banks. The DRAM includes the usual addressing and data path circuitry, as well as a refresh controller that refreshes the arrays in a manner that hides refreshes sufficiently that the DRAM can be used in place of an SRAM as a cache memory. Since only one of the arrays in each bank is refreshed at a time, the refresh controller is able to allow data to be written to the array that is not being refreshed. The refresh controller then causes the write data to be temporarily stored so that it can be written to the array of the refresh of the array has been completed. If neither array is being refreshed, the data are written to both arrays. Data are read from the arrays by first checking to determine if any of the arrays is being refreshed. If so, data are read from the array that is not being refreshed.

摘要翻译： 用于刷新动态随机存取存储器（“DRAM”）的方法和系统包括用于多个存储体中的每一个的一对存储器阵列。 DRAM包括通常的寻址和数据路径电路，以及刷新控制器，其以隐藏更充分的方式刷新阵列，使得DRAM可以用来代替SRAM作为高速缓冲存储器。 由于每次刷新每个存储体中只有一个阵列，所以刷新控制器能够将数据写入未刷新的数组。 然后，刷新控制器使得写入数据被临时存储，使得其可以被写入阵列的刷新的阵列已经完成。 如果两个数组都不被刷新，数据将被写入两个数组。 通过首先检查来确定数组是否被刷新，从数组中读取数据。 如果是这样，数据从数组中读取，没有被刷新。

公开(公告)号：US06274928B1

公开(公告)日：2001-08-14

申请号：US08852911

申请日：1997-05-08

申请人： Stephen L. Casper ,  Timothy J. Allen ,  Mark D. Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

发明人： Stephen L. Casper ,  Timothy J. Allen ,  Mark D. Durcan ,  Brian M. Shirley ,  Howard E. Rhodes

IPC分类号： H01L2352

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/1815 ,  H01L2924/00

摘要： A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

摘要翻译： 描述了16兆比特（224）或更大密度的单沉积层金属动态随机存取存储器（DRAM）部件，其允许适用于工业标准的300ml宽SOJ（小外形J翼）封装或TSOP （薄型，小外形封装），与以前的双金属沉积分层16兆位DRAM设计相比，速度损失很少或没有速度损失。 这是通过使用允许单个金属层信号路径的管芯架构来实现的，以及引线框架的新颖使用以去除芯片的大部分功率，从而允许较小的速度优化的DRAM。 使用单个沉积层金属导致较低的生产成本和较短的生产时间。

公开(公告)号：US06242782B1

公开(公告)日：2001-06-05

申请号：US09124283

申请日：1998-07-29

申请人： Stephen L. Casper ,  Brian M. Shirley ,  Kevin G. Duesman

发明人： Stephen L. Casper ,  Brian M. Shirley ,  Kevin G. Duesman

IPC分类号： H01L2994

CPC分类号： H01L21/765 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/10805 ,  Y10T307/839

摘要： The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

摘要翻译： 连接在半导体衬底中形成的相邻晶体管的非相关有源区的隔离栅的提供不需要额外的工艺步骤来提供相邻晶体管的有效隔离。 隔离栅极连接到参考，以确保未形成非相关活动区域之间的通道，并提供有效的隔离。 相邻的晶体管被​​交叉耦合以形成用于动态随机存取存储器件的读出放大器。

公开(公告)号：US5777937A

公开(公告)日：1998-07-07

申请号：US927360

申请日：1997-09-09

申请人： Brian M. Shirley

发明人： Brian M. Shirley

IPC分类号： G11C7/06 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/065

摘要： A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

公开(公告)号：US5657277A

公开(公告)日：1997-08-12

申请号：US636280

申请日：1996-04-23

申请人： Brian M. Shirley

发明人： Brian M. Shirley

IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C7/14 ,  G11C11/408 ,  G11C11/4099

CPC分类号： G11C11/4099 ,  G11C11/4085 ,  G11C7/14

摘要： Tracking circuitry is described for use in a memory device. The tracking circuitry be used to monitor word line voltages in a dynamic random access memory (DRAM) and includes a comparator circuit which compares a simulated word line signal to a digit line equilibrate bias voltage. The equilibrate bias voltage is generated using either memory column circuitry or a linear resistor voltage divider.

摘要翻译： 描述跟踪电路用于存储器件。 跟踪电路用于监视动态随机存取存储器（DRAM）中的字线电压，并且包括将模拟字线信号与数字线路平衡偏置电压进行比较的比较器电路。 使用存储器列电路或线性电阻分压器产生平衡偏置电压。