摘要:
A data storage system wherein a host computer is coupled to a bank of disk drives through an interface. The interface has a plurality of directors and a memory interconnected by a buss. The directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. The interface includes a plurality of ESCON adapters, a front end portion of the directors being coupled between the host computer and the busses through the ESCON adapters. Each one of such adapters includes a plurality of adapter ports each one being coupled to a corresponding port of the host computer. Each one of the adapters also includes a plurality of adapter board gate arrays and a plurality of optic interfaces. Each one of the optic interfaces is coupled between a corresponding one of the adapter port and a corresponding one of the adapter board gate arrays. Each coupled optic interfaces and gate array provides a corresponding one of a plurality of channels for the data. The adapter also includes a plurality of adapter board CPUs, each one being coupled to the adapter board gate arrays and the optic interface of a corresponding one of the channels. Each one of the CPUs controls the initiation and termination of the data passing through said corresponding one of the channels. Each one of the front end portion of the director boards includes a plurality of director board gate arrays and a plurality of EDACs. Each pair of the director board gate arrays is coupled between a corresponding pair of the adapter board gate arrays and a corresponding one of the EDACs. A plurality of director board CPUs is provided. Each one is coupled to a corresponding one of the adapter board CPUs. Each one of the director board CPUs is coupled to a corresponding one of the director board gate arrays to control the initiation and termination of a data transfer through such coupled one of the director gate arrays. A common state machine is coupled to the plurality of director gate arrays and the plurality of EDACs for arbitrating between the pair of director gate arrays coupled to the corresponding one of the EDACs for access to such corresponding one of the EDACs. Each one of the directors comprises: a plurality of dual port RAMs, each one being coupled to a corresponding one of the EDACs and to at least one of the busses. A second common state machine is coupled to the first common state machine and the plurality of dual port RAMs for arbitrating between the plurality of dual port RAMS for access to one the at least one of the busses.
摘要:
A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.
摘要:
A data storage system wherein a host computer is coupled to a bank of disk drives through an interface. The interface has a plurality of directors and a memory interconnected by a bus. The directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. The interface includes a plurality of ESCON adapters, a front end portion of the directors being coupled between the host computer and the busses through the ESCON adapters. Each one of such adapters includes a plurality of adapter ports each one being coupled to a corresponding port of the host computer. Each one of the adapters also includes a plurality of adapter board gate arrays and a plurality of optic interfaces. Each one of the optic interfaces is coupled between a corresponding one of the adapter port and a corresponding one of the adapter board gate arrays.
摘要:
A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.
摘要:
A system having a memory with a plurality of contiguous processor memory regions and a plurality of processors. Each one of such processors is associated with a corresponding one of the processor memory regions. Each one of such processors provides a plurality of sets of successive processor addresses. The addresses in each one of such sets has a successive series of used addresses and a successive series of reserve addresses. The last used address in each one of the sets is separated from the first used address in the next successive set of addresses by a gap of addresses, G. A common address translator is fed by virtual addresses and maps the virtual addresses fed thereto to the memory addresses, such mapping being in accordance with the gap G to map each one of the sets of used processor addresses provided by each of the processors into the corresponding one of the contiguous processor memory regions.
摘要:
A hardware emulation controller permits a high performance processor to be used with system circuitry that is configured for operation with a different processor. The hardware emulation controller is capable of modifying signals from the high performance processor for compatibility with the system circuitry. The hardware emulation controller is also capable of modifying signals from the system circuitry for compatibility with the high performance processor.
摘要:
A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.
摘要:
A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker.
摘要:
A system and method wherein a bus arbiter grants access to a bus to bus-coupled clients in order to provide access to a memory resource shared by the clients in response to “address retry” conditions induced by such clients. The bus arbiter provides access to the bus in response to whether one of the requesting clients experienced an “address retry” condition during its previous bus access. If such an address retry condition was experienced during its previous bus access, the bus arbiter grants such one of the requesting clients access to the bus at the earliest opportunity. Otherwise, the bus arbiter provides bus access to the requesting one, or ones, of the clients based on criteria independent of “address retry” conditions being induced on the bus.
摘要:
A method of transmitting data includes: A. receiving, at each of a plurality of data transmission devices of a transmitter, a data bit of a data word from a host; B. determining that a data word has been received from the host and asserting a data valid signal; C. transmitting the asserted data valid signal to a data valid register of a receiver including a plurality of data reception devices, each being coupled to a corresponding one of the plurality of data transmission devices of the transmitter; D. transmitting the data bit from each of the plurality of data transmission devices to the corresponding data reception device; E. inputting the data valid signal to each of the plurality of data reception devices to instruct the plurality of data reception devices to sample the data bit transmitted thereto from the corresponding data transmission device; wherein Step C occurs before Step D and Steps D and E occur substantially simultaneously.