公开(公告)号：US06787400B2

公开(公告)日：2004-09-07

申请号：US10346668

申请日：2003-01-16

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L21332

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

摘要翻译： 静电放电保护器件形成在衬底中，并且包含与掺杂剂浓度低于第一掺杂剂浓度的延伸漏极区相邻的第一掺杂剂浓度的漏区。 类似地，高掺杂源极区域邻接下掺杂源极延伸区域。 源极和漏极由氧化物区域横向界定并被绝缘层覆盖。 较低掺杂的区域通过在漏极的几乎平的底部表面电阻强制电流而不是弯曲的漏极延伸来防止静电放电事件期间的电荷拥挤。 此外，高度掺杂的掩埋层可以邻接渐变掺杂水平的区域。 通过调整分级区域和掩埋层的掺杂水平，预先选择衬底击穿电压。

公开(公告)号：US06593218B2

公开(公告)日：2003-07-15

申请号：US09927275

申请日：2001-08-09

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L21425

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

公开(公告)号：US06576960B2

公开(公告)日：2003-06-10

申请号：US10095640

申请日：2002-03-11

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

公开(公告)号：US06365937B1

公开(公告)日：2002-04-02

申请号：US09310538

申请日：1999-05-12

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device for integrated circuit is formed in a substrate and contains pad contact, rail contact and a deep oxide in a trench in the substrate which isolates pad and rail contacts. The substrate is doped with a first dopant type with a first concentration. A second dopant type in a first inner and a first outer region forms the pad contact; both regions are formed on the substrate. The first inner region is doped higher than the first outer region. Similarly a second dopant type in a second inner and a second outer region forms the rail contact; both regions are formed on the substrate. The second inner region is doped higher than the second outer region. Buried layers are formed of the first dopant type in a second concentration under the pad and rail contacts and under the deep oxide.

摘要翻译： 用于集成电路的静电放电保护装置形成在衬底中，并且在衬底中的沟槽中包含衬垫接触，轨道接触和深氧化物，隔离衬垫和轨道触点。 衬底掺杂有第一浓度的第一掺杂剂类型。 在第一内部和第一外部区域中的第二掺杂剂形式形成焊盘触点; 两个区域形成在基板上。 第一内部区域被掺杂高于第一外部区域。 类似地，在第二内部和第二外部区域中的第二掺杂剂形式形成轨道接触; 两个区域形成在基板上。 第二内部区域被掺杂高于第二外部区域。 掩埋层在第二浓度下由第一掺杂剂形成在焊盘和轨道触点下方以及深氧化物下方。

公开(公告)号：US06355508B1

公开(公告)日：2002-03-12

申请号：US09290720

申请日：1999-04-12

申请人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

发明人： Stephen R. Porter ,  Manny K. Ma ,  Stephen Casper ,  Kevin Duesman

IPC分类号： H01L21332

CPC分类号： H01L27/0266 ,  H01L27/0255 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

摘要翻译： 静电放电保护器件形成在衬底中，并且包含与掺杂剂浓度低于第一掺杂剂浓度的延伸漏极区相邻的第一掺杂剂浓度的漏区。 类似地，高掺杂源极区域邻接下掺杂源极延伸区域。 源极和漏极由氧化物区域横向界定并被绝缘层覆盖。 较低掺杂的区域通过在漏极的几乎平的底部表面电阻强制电流而不是弯曲的漏极延伸来防止静电放电事件期间的电荷拥挤。 此外，高度掺杂的掩埋层可以邻接渐变掺杂水平的区域。 通过调整分级区域和掩埋层的掺杂水平，预先选择衬底击穿电压。

公开(公告)号：US06600687B2

公开(公告)日：2003-07-29

申请号：US10253844

申请日：2002-09-23

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06353564B1

公开(公告)日：2002-03-05

申请号：US09735157

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C2900

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06335888B2

公开(公告)日：2002-01-01

申请号：US09735120

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06226210B1

公开(公告)日：2001-05-01

申请号：US09482716

申请日：2000-01-12

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a is plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06198676B1

公开(公告)日：2001-03-06

申请号：US09483266

申请日：2000-01-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。