公开(公告)号：US06255838B1

公开(公告)日：2001-07-03

申请号：US09567796

申请日：2000-05-09

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the same or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备上检测到相同或另一信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US06255837B1

公开(公告)日：2001-07-03

申请号：US09567632

申请日：2000-05-09

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey ,  Jason E. Graalum

IPC分类号： G01R3128

CPC分类号： G01R31/31701 ,  G01R31/2884

摘要： A test-mode latching circuit residing on an integrated circuit with test circuitry and operational circuitry has an enable state and a disable state. In the enable state, a test key is able to be latched so as to trigger a test mode. In the disable state, test key inputs are not latched and, thus, test modes are not entered. Initially, the circuit is readily enabled so that the IC can be tested upon fabrication. The circuit is locked in a disable state before external sale. A re-enable circuit is present to preclude inadvertent switching of the latching circuit back into the enable state during customer operation. Safeguards are implemented to avoid inadvertently re-enabling the latching circuit. To re-enable the latching circuit, an out-of-spec voltage is applied to an anti-fuse capacitor or programmable logic circuit while an out-of-spec voltage of the sane or another signal is detected at a field device. In one embodiment, the state switches to the enable state in response to the out-of-spec voltage. In alternative embodiments, an additional or subsequent signal, such as a prescribed clock pattern, occurs before the first circuit switches to the enable state.

摘要翻译： 驻留在具有测试电路和操作电路的集成电路上的测试模式锁存电路具有使能状态和禁止状态。 在使能状态下，可以锁存测试键以触发测试模式。 在禁用状态下，测试键输入不被锁存，因此不会输入测试模式。 最初，该电路容易启用，使IC可以在制造时进行测试。 电路在外部销售之前被锁定在禁用状态。 存在重启动电路，以防止在客户操作期间将锁存电路意外切换回使能状态。 实施保护措施以避免无意中重新启用锁存电路。 为了重新启用锁存电路，在现场设备处检测到合格或其他信号的超出规格的电压时，会将超出规格的电压施加到反熔丝电容器或可编程逻辑电路。 在一个实施例中，状态响应于超出规格的电压而切换到使能状态。 在替代实施例中，在第一电路切换到使能状态之前发生附加或后续信号，例如规定的时钟模式。

公开(公告)号：US06130834A

公开(公告)日：2000-10-10

申请号：US274932

申请日：1999-03-23

申请人： Patrick J. Mullarkey ,  Casey R. Kurth ,  Jason Graalum ,  Daryl L. Habersetzer

发明人： Patrick J. Mullarkey ,  Casey R. Kurth ,  Jason Graalum ,  Daryl L. Habersetzer

IPC分类号： G11C17/18 ,  G11C17/00

CPC分类号： G11C17/18

摘要： Circuitry for programming antifuse elements is provided which permits all antifuse elements in a bank to be programmed simultaneously, thereby enhancing the speed at which antifuse elements may be programmed. In one embodiment, a feedback circuit is associated with each antifuse element to stop the flow of current through the antifuse element once it is programmed. In another embodiment, circuitry is provided for generating a separate programming pulse for each antifuse element, which is selected for programming.

公开(公告)号：US6011731A

公开(公告)日：2000-01-04

申请号：US259221

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06834022B2

公开(公告)日：2004-12-21

申请号：US10717862

申请日：2003-11-18

申请人： Scott J. Derner ,  Casey R. Kurth ,  Daryl L. Habersetzer

发明人： Scott J. Derner ,  Casey R. Kurth ,  Daryl L. Habersetzer

IPC分类号： G11C700

CPC分类号： G11C11/40622 ,  G11C11/406

摘要： A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored automatically by the memory device during a memory operation mode or manually by a user during a programming mode.

摘要翻译： 存储器件包括地址选择电路，用于存储存储器单元的选定行的地址。 在刷新模式下，只刷新所选行的存储单元。 所选择的行的地址可以在存储器操作模式期间由存储器设备自动存储，或者在编程模式期间由用户手动存储。

公开(公告)号：US06650587B2

公开(公告)日：2003-11-18

申请号：US09988988

申请日：2001-11-19

申请人： Scott J. Derner ,  Casey R. Kurth ,  Daryl L. Habersetzer

发明人： Scott J. Derner ,  Casey R. Kurth ,  Daryl L. Habersetzer

IPC分类号： G11C700

CPC分类号： G11C11/40622 ,  G11C11/406

摘要： A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or automatically.

公开(公告)号：US5770480A

公开(公告)日：1998-06-23

申请号：US833863

申请日：1997-04-10

申请人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

发明人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

IPC分类号： H01L23/44 ,  H01L23/495 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49575 ,  H01L23/49537 ,  H01L23/49541 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L24/45 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107

摘要： A device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein a least one of the superimposed dice has at least one bond pad variably positioned on an active surface of the die. A plurality of lead fingers from a leadframe extend between the dice. The leadframe comprises at least one lead with leads of non-uniform length and configuration to attach to the differently positioned bond pads of the multiple die. An advantage of the present invention is that it allows dice with differing bond pad arrangements to be used in a superimposed configuration to increase circuit density, while eliminating the use of bond wires in such a configuration.

摘要翻译： 一种用于提高集成电路密度的装置和方法，包括至少一对叠加的骰子，其中所述叠加的骰子中的至少一个具有可变地定位在所述骰子的有效表面上的至少一个接合衬垫。 来自引线框架的多根引线指在芯片之间延伸。 引线框架包括至少一个具有不均匀长度和配置的引线的引线，以连接到多个管芯的不同定位的焊盘。 本发明的一个优点是，允许具有不同粘合垫布置的骰子以叠加配置使用以增加电路密度，同时消除在这种配置中使用接合线。

公开(公告)号：US5721703A

公开(公告)日：1998-02-24

申请号：US641114

申请日：1996-04-29

申请人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey

发明人： Daryl L. Habersetzer ,  Casey R. Kurth ,  Patrick J. Mullarkey

IPC分类号： G11C7/10 ,  G11C16/20 ,  G11C16/06

CPC分类号： G11C7/1045 ,  G11C16/20

摘要： An integrated circuit package includes an integrated circuit device that operates in more than one operational mode. The operational mode of the integrated circuit device is controlled by a mode select input. Examples of operational modes include fast page and block modes, two- and three-latency modes, and normal and test modes. A reprogrammable mode select circuit within the integrated circuit package produces a mode control signal that drives a mode select input of the integrated circuit device. The operational mode of the integrated circuit device then corresponds to the state of the mode select signal.

摘要翻译： 集成电路封装包括以多于一种操作模式操作的集成电路器件。 集成电路器件的工作模式由模式选择输入控制。 操作模式的示例包括快速页面和块模式，两种和三种延迟模式，以及正常和测试模式。 集成电路封装内的可再编程模式选择电路产生驱动集成电路器件的模式选择输入的模式控制信号。 然后，集成电路装置的工作模式对应于模式选择信号的状态。

公开(公告)号：US5677567A

公开(公告)日：1997-10-14

申请号：US664409

申请日：1996-06-17

申请人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

发明人： Manny Kin F. Ma ,  Jeffrey D. Bruce ,  Daryl L. Habersetzer ,  Gordon D. Roberts ,  James E. Miller

IPC分类号： H01L23/44 ,  H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49537 ,  H01L23/49541 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L24/45 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30107

摘要： A device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein at least one of the superimposed dice has at least one bond pad variably positioned on an active surface of the die. A plurality of lead fingers from a leadframe extend between the dice. The leadframe comprises at least one lead with leads of non-uniform length and configuration to attach to the differently positioned bond pads of the multiple dice. An advantage of the present invention is that it allows dice with differing bond pad arrangements to be used in a superimposed configuration to increase circuit density, while eliminating the use of bond wires in such a configuration.

摘要翻译： 一种用于增加集成电路密度的装置和方法，包括至少一对叠加的骰子，其中所述叠加的骰子中的至少一个具有可变地定位在所述骰子的有效表面上的至少一个接合衬垫。 来自引线框架的多根引线指在芯片之间延伸。 引线框架包括至少一个引线，引线具有不均匀的长度和结构，以连接到多个裸片的不同定位的焊盘。 本发明的一个优点是，允许具有不同粘合垫布置的骰子以叠加配置使用以增加电路密度，同时消除在这种配置中使用接合线。

公开(公告)号：US06882587B2

公开(公告)日：2005-04-19

申请号：US10883415

申请日：2004-06-30

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取多次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。