公开(公告)号：US5740349A

公开(公告)日：1998-04-14

申请号：US481927

申请日：1995-06-07

申请人： Robert N. Hasbun ,  Steven E. Wells

发明人： Robert N. Hasbun ,  Steven E. Wells

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/765

摘要： A controller for controlling associated circuitry which includes a microprocessor, read only memory for storing control processes to be run by the microprocessor for controlling the associated circuitry, random access memory, and means for accessing the associated circuitry, by a process which detects changes in the associated circuitry during operation of the associated circuitry, and writes those changes to the read only memory so that they are available to the controller should power be lost during the operation of the associated circuitry.

摘要翻译： 一种用于控制相关电路的控制器，其包括微处理器，只读存储器，用于存储由微处理器运行的控制过程，用于控制相关联的电路，随机存取存储器和用于访问相关电路的装置，该过程检测 并且将这些改变写入只读存储器，使得它们对于控制器可用，在相关电路的操作期间应该丢失电源。

公开(公告)号：US5448577A

公开(公告)日：1995-09-05

申请号：US969464

申请日：1992-10-30

申请人： Steven E. Wells ,  Robert N. Hasbun

发明人： Steven E. Wells ,  Robert N. Hasbun

IPC分类号： G06F11/10 ,  H03M13/09 ,  H03M13/00

CPC分类号： G06F11/1068 ,  H03M13/09

摘要： A method for utilizing a cyclical redundancy check value with an identification field stored in memory which is constantly changing between testing of the cyclical redundancy check value. In order to allow the use of a cyclical redundancy check value with a field which constantly varies as does the field in a flash EEPROM memory array, various portions of the field are masked to the cyclical redundancy check and additional reliability checks are utilized to assure that those portions which are masked remain reliable.

摘要翻译： 一种用于利用存储在存储器中的识别字段的循环冗余校验值的方法，所述识别字段在循环冗余校验值的测试之间不断变化。 为了允许使用具有与闪存EEPROM存储器阵列中的字段不断变化的字段的循环冗余校验值，该字段的各个部分被掩蔽到循环冗余校验，并且使用附加的可靠性检查来确保 那些被屏蔽的部分保持可靠。

公开(公告)号：US5357475A

公开(公告)日：1994-10-18

申请号：US969466

申请日：1992-10-30

申请人： Robert N. Hasbun ,  Steven E. Wells ,  Richard P. Garner

发明人： Robert N. Hasbun ,  Steven E. Wells ,  Richard P. Garner

IPC分类号： G11C16/10 ,  G11C16/16 ,  G11C29/00 ,  G11C11/34

CPC分类号： G11C16/16 ,  G11C16/102 ,  Y10S707/99953 ,  Y10S707/99957

摘要： A process for releasing sectors of a flash EEPROM memory array which includes a plurality of individually erasable blocks and stores sectors of data in such blocks with a header providing a logical sector number, an indication of validity of data stored, and an indication of whether data is stored with the header. The process includes the steps of finding the header of a sector with data to be released, setting the indication of validity of the data stored to indicate that the data is invalid, and writing a new header for the sector to a new position in the array without data and with an indication that data is not attached.

摘要翻译： 一种用于释放快闪EEPROM存储器阵列的扇区的过程，其包括多个单独可擦除块，并且在这种块中存储具有提供逻辑扇区号的报头，存储的数据的有效性的指示以及数据的指示 与标题一起存储。 该过程包括以下步骤：用要发布的数据找出扇区的头部，设置存储的数据的有效性的指示，以指示数据无效，以及将扇区的新头部写入阵列中的新位置 没有数据，并且没有附加数据的指示。

公开(公告)号：US5867721A

公开(公告)日：1999-02-02

申请号：US978998

申请日：1997-11-28

申请人： Mark P. Leinwander ,  Steven E. Wells ,  Robert N. Hasbun

发明人： Mark P. Leinwander ,  Steven E. Wells ,  Robert N. Hasbun

IPC分类号： G06F12/06 ,  G06F12/08

CPC分类号： G06F12/06

摘要： A circuit for selecting a select line from a plurality of first and second select lines is described. Each of an array of integrated circuit (IC) packages is coupled to (1) one of the first select lines and (2) at least one of the second select lines. The circuit includes a decoder for decoding a select data to select the select line, and circuitry for modifying the select data before the select data is applied to the decoder when each of the second select lines is not coupled to an IC device within each of the IC packages to ensure that the select line is not one of the second select lines. When each of the first and second select lines is coupled to an IC device within each of the IC packages, the circuitry for modifying does not modify the select data. A method for selecting a selected IC device within a selected IC package of an array of IC packages is also described.

摘要翻译： 描述用于从多个第一和第二选择线选择选择线的电路。 集成电路（IC）封装的阵列中的每一个耦合到（1）第一选择线之一和（2）至少一个第二选择线。 该电路包括用于对选择数据进行解码以选择选择线的解码器，以及用于当每个第二选择线未耦合到每个第一选择线内的IC器件时，在选择数据被施加到解码器之前修改选择数据的电路 IC封装，以确保选择线不是第二选择线之一。 当第一和第二选择线中的每一个耦合到每个IC封装内的IC器件时，用于修改的电路不修改选择数据。 还描述了用于在IC封装阵列的选定IC封装内选择所选IC器​​件的方法。

公开(公告)号：US5581723A

公开(公告)日：1996-12-03

申请号：US20204

申请日：1993-02-19

申请人： Robert N. Hasbun ,  Steven E. Wells

发明人： Robert N. Hasbun ,  Steven E. Wells

IPC分类号： G06F3/06 ,  G06F11/14 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F3/0601 ,  G06F12/0246 ,  G06F11/1435 ,  G06F2003/0694

摘要： A method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory cells and in which each of the blocks of memory cells has stored thereon data regarding management of the array during a cleanup process in which valid data stored in a first block is written to another block of the array, and then the first block is erased. The process includes the steps of storing data regarding management of the array from the first block in random access memory and, in an enhanced process, on another block before erasure of the first block. The data may then be rewritten to the first block after the erase. With the enhanced process, a special identification is provided to the data regarding the management of the array stored on another block which is outside the normal identification range for the host computer so that the specially identified data is not lost during a power loss during an erase process and may be detected after power is restored to the system.

摘要翻译： 一种用于将快速EEPROM存储器阵列中的管理数据可靠地存储的方法，该阵列被划分为多个可单独擦除的存储器单元块，其中存储单元块中的每个块已经存储有关于在一个 清除过程，其中存储在第一块中的有效数据被写入阵列的另一个块，然后第一块被擦除。 该处理包括以下步骤：在第一块的擦除之前，将来自第一块的阵列的管理的数据存储在随机存取存储器中，并且在增强的处理中存储在另一个块上。 然后可以在擦除之后将数据重写到第一块。 通过增强处理，对存储在另一个块上的阵列的管理数据提供了特殊的标识，该数组在主计算机的正常识别范围之外，使得在擦除期间的功率损耗期间特殊识别的数据不会丢失 并且可以在电力恢复到系统之后被检测到。

公开(公告)号：US6014755A

公开(公告)日：2000-01-11

申请号：US700676

申请日：1996-08-12

申请人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

发明人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

IPC分类号： G11C17/00 ,  G06F11/00 ,  G06F11/10 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/765 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/88 ,  G11C2029/0409

摘要： A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

摘要翻译： 一种用于监视闪存阵列的操作的方法，所述闪速存储器阵列被划分成单独的可擦除存储块，以便确保存储在阵列中的数据的完整性，其中每个读取或写入操作被验证以检测可能在操作中发生的错误 包括以下步骤：每当发生错误以进行错误发生以尝试至少一次重试操作以确定该错误是否可重复时，如果该错误被发现是可重复的，则应该从该块中删除指示有效数据的块，从该块中删除有效信息 如果发现错误是可重复的，并且从操作中移除具有可重复错误的块，则阻塞。

公开(公告)号：US5577194A

公开(公告)日：1996-11-19

申请号：US511990

申请日：1995-08-07

申请人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

发明人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

IPC分类号： G11C17/00 ,  G06F11/00 ,  G06F11/10 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04 ,  G01R31/28

CPC分类号： G11C29/765 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/88 ,  G11C2029/0409

摘要： A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

公开(公告)号：US5473753A

公开(公告)日：1995-12-05

申请号：US969749

申请日：1992-10-30

申请人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

发明人： Steven E. Wells ,  Eric J. Magnusson ,  Robert N. Hasbun

IPC分类号： G11C17/00 ,  G06F11/00 ,  G06F11/10 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/765 ,  G06F11/1068 ,  G11C29/4401 ,  G11C29/88 ,  G11C2029/0409

摘要： A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.

公开(公告)号：US06401160B1

公开(公告)日：2002-06-04

申请号：US09282598

申请日：1999-03-31

申请人： Deborah L. See ,  Robert N. Hasbun

发明人： Deborah L. See ,  Robert N. Hasbun

IPC分类号： G06F1206

CPC分类号： G06F12/0223 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7206

摘要： A method of moving a boundary in a nonvolatile memory is disclosed. The method comprises identifying a boundary location in the nonvolatile memory. The boundary location comprises a position between a first block of a first type and a second block of a second type. The method also comprises allocating objects from a last block of the first type to a second block of the first type. Additionally, the method comprises erasing the last block of the first type.

摘要翻译： 公开了一种在非易失性存储器中移动边界的方法。 该方法包括识别非易失性存储器中的边界位置。 边界位置包括第一类型的第一块和第二类型的第二块之间的位置。 该方法还包括将对象从第一类型的最后块分配到第一类型的第二块。 另外，该方法包括擦除第一类型的最后一个块。

公开(公告)号：US5875477A

公开(公告)日：1999-02-23

申请号：US577742

申请日：1995-12-22

申请人： Robert N. Hasbun ,  Daniel H. Leemann

发明人： Robert N. Hasbun ,  Daniel H. Leemann

IPC分类号： G06F11/10 ,  G11C29/00 ,  G06F12/16 ,  G06F11/08

CPC分类号： G11C29/765 ,  G06F11/1068

摘要： A method of accessing a memory includes the step of partitioning the memory into a plurality of partitions. A primary logical identifier is stored in the memory to identify each partition. A redundant secondary logical identifier is also stored in the memory to identify each partition. In response to a requested partition number identifying a partition to access, at least one partition of data is located using a first stored logical identifier formed from a portion of each of the primary and secondary logical identifiers. The at least one partition of data is then identified using a second stored logical identifier formed from a portion of at least one of the primary and secondary logical identifiers. In one embodiment, a first error detection code (EDC) stored in the header is used to validate the partition data. If an error is detected, the validity of the partition data is tested using an EDC computed by ANDing the first EDC and a second EDC stored in the header. During a clean-up operation, a header is selected from a block targeted for clean-up. The first and second stored logical identifiers in the selected header are compared with each other. If there is not a match, then validation is performed using the ANDed value of the first and second stored logical sector number. In one embodiment, the memory is a flash electrically erasable programmable read only memory. In one embodiment, the partitions are sectors and the identifiers are sector numbers.

摘要翻译： 访问存储器的方法包括将存储器分割成多个分区的步骤。 主逻辑标识符存储在存储器中以识别每个分区。 冗余辅助逻辑标识符也存储在存储器中以识别每个分区。 响应于识别要访问的分区的所请求的分区号，使用从每个主逻辑标识符和辅助逻辑标识符的一部分形成的第一存储的逻辑标识符来定位至少一个数据分区。 然后使用从主逻辑标识符和次逻辑标识符中的至少一个的一部分形成的第二存储的逻辑标识符来识别数据的至少一个分区。 在一个实施例中，存储在报头中的第一错误检测码（EDC）用于验证分区数据。 如果检测到错误，则使用通过对存储在报头中的第一EDC和第二EDC进行AND运算的EDC来测试分区数据的有效性。 在清理操作期间，从用于清理的块中选择一个标题。 将所选择的报头中的第一和第二存储逻辑标识符彼此进行比较。 如果不匹配，则使用第一和第二存储的逻辑扇区号的ANDed值来执行验证。 在一个实施例中，存储器是闪存电可擦除可编程只读存储器。 在一个实施例中，分区是扇区，标识符是扇区号。