公开(公告)号：US07183175B2

公开(公告)日：2007-02-27

申请号：US11172707

申请日：2005-07-01

申请人： Steven John Koester ,  Klaus Dietrich Beyer ,  Michael John Hargrove ,  Kern Rim ,  Kevin Kok Chan

发明人： Steven John Koester ,  Klaus Dietrich Beyer ,  Michael John Hargrove ,  Kern Rim ,  Kevin Kok Chan

IPC分类号： H01L21/762

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/78687

摘要： A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

摘要翻译： 公开了用于隔离电子设备的结构和用于制造该结构的方法。 电子器件在包括在应变Si层下面的基于SiGe的层的衬底中被处理。 隔离结构包括从衬底顶表面向下延伸并且穿透到基于SiGe的层中的沟槽，在衬底中形成侧壁。 外延Si衬垫选择性地沉积在沟槽侧壁上，随后被热氧化。 沟槽填充有沟槽电介质，其在衬底顶表面上方突出。

公开(公告)号：US06335262B1

公开(公告)日：2002-01-01

申请号：US09231617

申请日：1999-01-14

申请人： Scott W. Crowder ,  Anthony Gene Domenicucci ,  Liang-Kai Han ,  Michael John Hargrove ,  Paul Andrew Ronsheim

发明人： Scott W. Crowder ,  Anthony Gene Domenicucci ,  Liang-Kai Han ,  Michael John Hargrove ,  Paul Andrew Ronsheim

IPC分类号： H01L2131

CPC分类号： H01L21/823462 ,  H01L21/31662 ,  Y10S148/116 ,  Y10S148/163 ,  Y10S438/981

摘要： A semiconductor structure having silicon dioxide layers of different thicknesses is fabricated by forming a sacrificial silicon dioxide layer on the surface of a substrate; implanting nitrogen ions through the sacrificial silicon dioxide layer into first areas of the semiconductor substrate; implanting chlorine and/or bromine ions through the sacrificial silicon dioxide layer into second areas of the semiconductor substrate where silicon dioxide having the highest thickness is to be formed; removing the sacrificial silicon dioxide layer; and then growing a layer of silicon dioxide on the surface of the semiconductor substrate. The growth rate of the silicon dioxide will be faster in the areas containing the chlorine and/or bromine ions and therefore the silicon dioxide layer will be thicker in those regions as compared to the silicon dioxide layer in the regions not containing the chlorine and/or bromine ions. The growth rate of the silicon dioxide will be slower in the areas containing the nitrogen ions and therefore the silicon dioxide layer will be thinner in those regions as compared to the silicon dioxide layer in the regions not containing the nitrogen ions. Also provided are structures obtained by the above process.

摘要翻译： 通过在基板的表面上形成牺牲二氧化硅层来制造具有不同厚度的二氧化硅层的半导体结构; 将氮离子通过牺牲二氧化硅层注入到半导体衬底的第一区域中; 将氯和/或溴离子通过牺牲二氧化硅层注入到要形成具有最高厚度的二氧化硅的半导体衬底的第二区域中; 去除牺牲二氧化硅层; 然后在半导体衬底的表面上生长一层二氧化硅。 在含有氯和/或溴离子的区域中，二氧化硅的生长速度将更快，因此与不含氯和/或溴离子的区域中的二氧化硅层相比，二氧化硅层在这些区域中将更厚。 溴离子。 与含氮离子的区域相比，在含氮离子的区域中，二氧化硅的生长速度较慢，因此与这些区域的二氧化硅层相比，二氧化硅层较薄。 还提供了通过上述方法获得的结构。

公开(公告)号：US5731941A

公开(公告)日：1998-03-24

申请号：US525110

申请日：1995-09-08

申请人： Michael John Hargrove ,  Steven Howard Voldman

发明人： Michael John Hargrove ,  Steven Howard Voldman

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0251

摘要： An enhanced electrostatic discharge suppression circuit is disclosed for protecting integrated circuit chips from electrostatic discharges or other potentially damaging voltage transients on an input/output pad. The suppression circuit includes a discharge circuit, electrically coupled to the input/output pad, having a diode comprising a diffusion in a substrate well formed in a substrate. The diffusion is connected to the input/output pad of the integrated circuit. A capacitor is locally provided to couple the substrate well to the substrate. The capacitor is sized to maintain the diode in a forward-bias mode during the electrostatic discharge event, thereby facilitating dissipating of the electrostatic discharge. The capacitor comprises a trench capacitor, which depending upon the configuration, may function as a guard ring for the discharge circuit. Certain beneficial parasitic effects are also discussed in association with integration of a trench capacitor into the suppression circuit.

摘要翻译： 公开了一种增强的静电放电抑制电路，用于保护集成电路芯片免受静电放电或输入/输出焊盘上的其他潜在的破坏性电压瞬变。 抑制电路包括电耦合到输入/输出焊盘的放电电路，其具有二极管，该二极管包括在衬底中形成的衬底中的扩散。 扩散连接到集成电路的输入/输出焊盘。 局部提供电容器以将衬底阱与衬底耦合。 电容器的尺寸设计成在静电放电事件期间将二极管保持在正向偏压模式，从而有助于消除静电放电。 电容器包括沟槽电容器，其取决于配置，可用作放电电路的保护环。 还讨论了将沟槽电容器集成到抑制电路中的一些有益的寄生效应。