公开(公告)号：US07183175B2

公开(公告)日：2007-02-27

申请号：US11172707

申请日：2005-07-01

申请人： Steven John Koester ,  Klaus Dietrich Beyer ,  Michael John Hargrove ,  Kern Rim ,  Kevin Kok Chan

发明人： Steven John Koester ,  Klaus Dietrich Beyer ,  Michael John Hargrove ,  Kern Rim ,  Kevin Kok Chan

IPC分类号： H01L21/762

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/78687

摘要： A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

摘要翻译： 公开了用于隔离电子设备的结构和用于制造该结构的方法。 电子器件在包括在应变Si层下面的基于SiGe的层的衬底中被处理。 隔离结构包括从衬底顶表面向下延伸并且穿透到基于SiGe的层中的沟槽，在衬底中形成侧壁。 外延Si衬垫选择性地沉积在沟槽侧壁上，随后被热氧化。 沟槽填充有沟槽电介质，其在衬底顶表面上方突出。

公开(公告)号：US20120149159A1

公开(公告)日：2012-06-14

申请号：US13397865

申请日：2012-02-16

申请人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

发明人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

公开(公告)号：US07888264B2

公开(公告)日：2011-02-15

申请号：US12814942

申请日：2010-06-14

申请人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

发明人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

IPC分类号： H01L21/44

CPC分类号： H01L29/66507 ,  H01L29/6653 ,  H01L29/7833

摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

摘要翻译： 提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。 根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。 此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

公开(公告)号：US07714358B2

公开(公告)日：2010-05-11

申请号：US11672599

申请日：2007-02-08

申请人： Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

发明人： Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.

摘要翻译： 公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。 在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。 在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。 因此，可以更深地形成碳注入区域。 完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。 此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

公开(公告)号：US20100112766A1

公开(公告)日：2010-05-06

申请号：US12685027

申请日：2010-01-11

申请人： Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

发明人： Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.

摘要翻译： 公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。 在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。 在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。 因此，可以更深地形成碳注入区域。 完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。 此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

公开(公告)号：US07682915B2

公开(公告)日：2010-03-23

申请号：US12100644

申请日：2008-04-10

申请人： Huajie Chen ,  Judson R. Holt ,  Kern Rim ,  Dominic J. Schepis

发明人： Huajie Chen ,  Judson R. Holt ,  Kern Rim ,  Dominic J. Schepis

IPC分类号： H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.

摘要翻译： 本发明的实施例提供了一种用于具有非常低的温度选择性外延的预外延一次性间隔物集成方案的方法等，以增强器件性能。 更具体地，一种方法是通过在衬底上形成第一栅极和第二栅极开始的。 接下来，在第一和第二栅极上形成氧化物层; 并且在氧化物层上形成氮化物层。 接近第一栅极的氮化物层的部分，靠近第一栅极的氧化物层的部分以及靠近第一栅极的衬底的部分被去除，以便形成靠近第一栅极的源极和漏极。 接下来，该方法去除氮化物层的剩余部分，包括暴露氧化物层的剩余部分。 去除氮化物层的剩余部分仅暴露氧化物层和源极和漏极凹槽的剩余部分。

公开(公告)号：US07605077B2

公开(公告)日：2009-10-20

申请号：US11308486

申请日：2006-03-29

申请人： William K. Henson ,  Kern Rim ,  Jack A. Mandelman

发明人： William K. Henson ,  Kern Rim ,  Jack A. Mandelman

IPC分类号： H01L21/40 ,  H01L29/45

CPC分类号： H01L21/823443 ,  H01L21/82345 ,  H01L21/823835 ,  H01L21/823842

摘要： An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.

摘要翻译： 提供了与源极/漏极区域同时实现nFET和pFET栅电极的全硅化（FUSI）的集成方案。 栅电极的FUSI消除了多晶硅栅电极观察到的栅耗尽问题。 此外，本发明的集成方案刚好在硅化之前产生栅电极的不同硅厚度。 本发明的该特征允许制造具有针对特定器件区域定制的带边缘功能函数的nFET和pFET。

公开(公告)号：US20090181508A1

公开(公告)日：2009-07-16

申请号：US12014934

申请日：2008-01-16

申请人： Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

发明人： Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A method forms a gate stack over a channel region of a substrate and then forms disposable spacers on sides of the gate stack. Trenches are then recessed in regions of the substrate not protected by the gate stack and the disposable spacers. Carbon-doped Silicon lattice structures are then formed in the trenches. During the forming of the Carbon-doped Silicon lattice structures Carbon atoms can be positioned in any substitutional sites within the lattice structures. The Carbon-doped Silicon lattice structures are then amorphized by implantation of an amorphizing species. An annealing process then recrystallizes the amorphized regions by solid-phase epitaxy regrowth to form the source and drain regions. During the annealing, a majority of Carbon atoms are substitutionally incorporated into a Silicon lattice of the source and drain regions to provide tensile stress to the channel region.

摘要翻译： 一种方法在衬底的通道区域上形成栅极堆叠，然后在栅极叠层的侧面上形成一次性间隔物。 沟槽然后凹陷在不被栅极堆叠和一次性间隔件保护的衬底的区域中。 然后在沟槽中形成碳掺杂的硅晶格结构。 在形成碳掺杂硅晶格结构期间，碳原子可以位于晶格结构内的任何取代位置。 然后通过植入非晶化物质将碳掺杂的硅晶格结构非晶化。 退火工艺然后通过固相外延再生长再结晶非晶化区域以形成源区和漏区。 在退火期间，大多数碳原子被替代地并入到源极和漏极区域的硅晶格中，以向沟道区域提供拉伸应力。

公开(公告)号：US07524740B1

公开(公告)日：2009-04-28

申请号：US12108917

申请日：2008-04-24

申请人： Yaocheng Liu ,  Devendra Kumar Sadana ,  Kern Rim

发明人： Yaocheng Liu ,  Devendra Kumar Sadana ,  Kern Rim

IPC分类号： H01L21/36 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/84

摘要： A method of forming a localized region of relaxed Si in a layer of strained Si arranged within a strained silicon directly on insulator (SSDOI) semiconductor substrate is provided by the invention. The strained Si layer is formed on a buried oxide (BOX) layer disposed on a Si substrate base. The method includes depositing a nitride hard mask pattern above a region of the strained Si layer in which enhanced electron mobility is desired, leaving an unmasked region within the strained Si layer, and carrying out various other processing steps to modify and relax the unmasked portion of the strained region. The method includes growing an EPI SiGe region upon the unmasked region using pre-amorphization implantation, and forming a buried amorphous SiGe region in a portion of the EPI SiGe region, and an amorphous Si region, below the amorphous SiGe region. Then, using SPE regrowth, modifying the amorphous SiGe and amorphous Si regions to realize an SPE SiGe region and relaxed SPE Si layer. The SiGe region and the SPE SiGe region are etched, leaving the relaxed SPE Si region above the buried oxide layer. The nitride pattern is stripped.

摘要翻译： 本发明提供了一种在布置在直接绝缘体（SSDOI）半导体衬底的应变硅中的应变Si层中形成弛豫Si局部区域的方法。 应变Si层形成在设置在Si衬底基底上的掩埋氧化物（BOX）层上。 该方法包括在需要增强的电子迁移率的应变Si层的区域之上沉积氮化物硬掩模图案，在应变Si层内留下未掩模的区域，并执行各种其它处理步骤以修饰和松弛未曝光部分 紧张区域。 该方法包括使用预非晶化注入在未掩模区域上生长EPI SiGe区域，以及在非晶SiGe区域的一部分EPI SiGe区域和非晶Si区域内形成掩埋非晶SiGe区域。 然后，使用SPE再生长，改性非晶SiGe和非晶Si区，实现SPE SiGe区和松弛的SPE Si层。 蚀刻SiGe区域和SPE SiGe区域，在掩埋氧化物层上方留下松弛的SPE Si区域。 剥离氮化物图案。

公开(公告)号：US07485518B2

公开(公告)日：2009-02-03

申请号：US11684855

申请日：2007-03-12

申请人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

发明人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

IPC分类号： H01L21/336

CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。