摘要:
A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle.
摘要:
A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle.
摘要:
A method of dynamically controlling a central processing unit is disclosed. The method may include determining when a CPU enters a steady state, calculating an optimal frequency for the CPU when the CPU enters a steady state, guaranteeing a steady state CPU utilization, and guaranteeing a steady state CPU utilization deadline.
摘要:
A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.
摘要:
A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.
摘要:
A method of dynamically controlling power within a multicore central processing unit is disclosed and includes executing a plurality of virtual cores, virtually executing one or more tasks, one or more threads, or a combination thereof at the virtual cores, and physically executing one or more tasks, one or more threads, or a combination thereof at a zeroth physical core. The method may further include receiving a degree of parallelism in a workload of a plurality of virtual cores and determining whether the degree of parallelism in the workload of the virtual cores is equal to a first wake condition.
摘要:
A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.
摘要:
A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition.
摘要:
A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.
摘要:
A method of controlling core clocks in a multicore central processing unit is disclosed and may include executing a zeroth dynamic clock and voltage scaling (DCVS) algorithm on a zeroth core and executing a first DCVS algorithm on a first core. The zeroth DCVS algorithm may operable to independently control a zeroth clock frequency associated with the zeroth core and the first DCVS algorithm may be operable to independently control a first clock frequency associated with the first core.