公开(公告)号：US06414896B1

公开(公告)日：2002-07-02

申请号：US09905376

申请日：2001-07-13

申请人： Su-a Kim ,  Byung-sick Moon

发明人： Su-a Kim ,  Byung-sick Moon

IPC分类号： G11C800

CPC分类号： G11C29/808 ,  G11C29/846

摘要： A semiconductor memory device having a column redundancy scheme for improving redundancy efficiency includes sub memory blocks, a redundancy memory block, global data input output lines respectively associated with the sub memory blocks, a redundancy global data input output line and switches. Each of the sub memory blocks has a plurality of memory cells. The redundancy memory block has a plurality of redundancy memory cells. The data of selected memory cells of a sub memory block are transmitted to a corresponding global data input output line. The data of selected redundancy memory cells of the redundancy memory block are transmitted to the redundancy global data input output line. A switch switches the global data input output line to the redundancy global data input output line if a memory cell connected to the global data input output line is defective.

摘要翻译： 具有用于提高冗余效率的列冗余方案的半导体存储器件包括子存储块，冗余存储块，分别与子存储块相关联的全局数据输入输出线，冗余全局数据输入输出线和开关。 每个子存储块具有多个存储单元。 冗余存储块具有多个冗余存储单元。 子存储器块的所选存储单元的数据被发送到相应的全局数据输入输出线。 冗余存储器块的所选择的冗余存储单元的数据被发送到冗余全局数据输入输出线。 如果连接到全局数据输入输出线的存储单元发生故障，则A开关将全局数据输入输出线切换到冗余全局数据输入输出线。

公开(公告)号：US06366155B1

公开(公告)日：2002-04-02

申请号：US09613367

申请日：2000-07-10

申请人： Byung-sick Moon ,  Mi-seon Kang ,  Ho-sung Song

发明人： Byung-sick Moon ,  Mi-seon Kang ,  Ho-sung Song

IPC分类号： G05F110

CPC分类号： H03K5/1534

摘要： Reference voltage regulators and methods for integrated circuit output driver systems generate an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to an output enable signal. Preferably, sufficient initial supplementary current is generated to compensate for an initial drop in the reference voltage that is generated by a reference voltage generator upon initial activation of the output driver system. Reference voltage generators according to embodiments of the invention may be included in an integrated circuit output driver system that is responsive to a reference voltage and to an output enable signal, and that varies in current drive capability in response to a current drive control signal. These embodiments of reference voltage regulators include a reference voltage generator that generates the reference voltage for the integrated circuit output driver system. A supplementary current generator generates an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to the output enable signal. In some embodiments, the supplementary current generator generates a fixed initial supplementary current for the integrated circuit output driver system. In other embodiments, the supplementary current generator generates a variable initial supplementary current for the integrated circuit output driver system at the reference voltage for the predetermined time period in response to the output enable signal, and that varies in response to the current drive control signal.

摘要翻译： 用于集成电路输出驱动器系统的参考电压调节器和方法响应于输出使能信号在预定时间周期内以参考电压产生集成电路输出驱动器系统的初始辅助电流。 优选地，产生足够的初始辅助电流以补偿在初始激活输出驱动器系统时由参考电压发生器产生的参考电压的初始下降。 根据本发明的实施例的参考电压发生器可以包括在响应于参考电压和输出使能信号的集成电路输出驱动器系统中，并且响应于当前驱动控制信号而在电流驱动能力中变化。 参考电压调节器的这些实施例包括产生用于集成电路输出驱动器系统的参考电压的参考电压发生器。 辅助电流发生器响应于输出使能信号，在预定时间周期内以参考电压产生用于集成电路输出驱动器系统的初始辅助电流。 在一些实施例中，辅助电流发生器为集成电路输出驱动器系统产生固定的初始辅助电流。 在其他实施例中，辅助电流发生器响应于输出使能信号而在预定时间段内以参考电压产生用于集成电路输出驱动器系统的可变初始辅助电流，并且响应于当前驱动控制信号而变化。

公开(公告)号：US06636451B2

公开(公告)日：2003-10-21

申请号：US10112003

申请日：2002-03-28

申请人： Duk-ha Park ,  Byung-sick Moon

发明人： Duk-ha Park ,  Byung-sick Moon

IPC分类号： G11C700

CPC分类号： G05F1/465

摘要： A semiconductor memory device internal voltage generator and internal voltage generating method are disclosed. The device and method are capable of supplying a uniform amount of electric charge and generating a stable internal voltage, despite variations in an external voltage. The internal voltage generator includes a PMOS driving transistor having a source connected to the external voltage, a gate connected to a driving signal, and a drain that supplies the internal voltage. The interval voltage generator also includes a driving signal generator that generates the driving signal in response to a control signal. The driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level despite variations in the external voltage.

公开(公告)号：US06326833B1

公开(公告)日：2001-12-04

申请号：US09430365

申请日：1999-10-28

申请人： Byung-sick Moon

发明人： Byung-sick Moon

IPC分类号： G05F110

CPC分类号： H02M3/073 ,  H02M2003/077

摘要： A highly effective charge pump circuit includes a pulse generator for generating a pulse signal in response to a control signal, a first voltage pumping unit for generating a first high voltage in response to the control signal and the pulse signal, a second voltage pumping unit for generating a second high voltage of the same level as the first high voltage in response to the control signal and the pulse signal, and a voltage transmitting unit that receives and outputs first high voltage when the second high voltage is applied. The charge pump obtains a high voltage using NMOS transistors.

摘要翻译： 高效电荷泵电路包括响应于控制信号产生脉冲信号的脉冲发生器，用于响应于控制信号和脉冲信号产生第一高电压的第一电压泵送单元，用于 响应于控制信号和脉冲信号产生与第一高电压相同电平的第二高电压;以及电压发送单元，其在施加第二高电压时接收并输出第一高电压。 电荷泵使用NMOS晶体管获得高电压。

公开(公告)号：US06219298B1

公开(公告)日：2001-04-17

申请号：US09487965

申请日：2000-01-18

申请人： Nak-won Hur ,  Byung-sick Moon

发明人： Nak-won Hur ,  Byung-sick Moon

IPC分类号： G11C800

CPC分类号： G11C8/10 ,  G11C8/18

摘要： High speed address decoders may include a predecoder and a main decoder that are both responsive to a control signal. The predecoder switches from an active state to an inactive state in response to a transition of the control signal from a first logic state to a second logic state. Conversely, the main decoder commences switching from an inactive state to an active state simultaneously with the transition of the control signal from the first logic state to the second logic state. The predecoder may generate a predecoded address signal while the control signal is in the first logic state, which may then be decoded by the main decoder to activate a line enable signal when the control signal transitions to the second logic state. As a result, address decoding speed may be improved thereby facilitating higher speed operation of an integrated circuit memory device.

摘要翻译： 高速地址解码器可以包括既对响应于控制信号的预解码器和主解码器。 响应于控制信号从第一逻辑状态到第二逻辑状态的转变，预解码器从活动状态切换到非活动状态。 相反，主解码器从控制信号从第一逻辑状态转换到第二逻辑状态同时开始从非活动状态切换到活动状态。 预解码器可以在控制信号处于第一逻辑状态时产生预解码的地址信号，然后可以由主解码器解码，以在控制信号转换到第二逻辑状态时激活线路使能信号。 结果，可以提高地址解码速度，从而便于集成电路存储器件的高速运行。

公开(公告)号：US06762948B2

公开(公告)日：2004-07-13

申请号：US10268592

申请日：2002-10-10

申请人： Kye-hyun Kyun ,  Byung-sick Moon

发明人： Kye-hyun Kyun ,  Byung-sick Moon

IPC分类号： G11C502

CPC分类号： G11C7/10 ,  G11C2207/105 ,  G11C2207/2254

摘要： A semiconductor memory device having first and second memory architectures with different structures and allowing the possibility of selecting any one of the first and second memory architectures using a selection process and a memory system using the semiconductor memory device are provided. The first memory architecture has p banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the banks, and n/2 data terminals DQ. The second memory architecture has p banks, a page size of m bytes, and n data terminals. The option process may be realized by a bonding, a mask pattern, or a fuse. In a memory device, the page size and the number of memory banks are adjusted by a design option. Thus, the memory architecture is modified, redundancy flexibility is increased and power consumption is reduced.

摘要翻译： 一种具有不同结构的第一和第二存储器体系结构的半导体存储器件，并且允许使用选择处理和使用半导体存储器件的存储器系统来选择第一和第二存储器架构中的任何一个的可能性。 第一存储器架构具有p个存储体，连接到每个存储体中的一个字线的m / 2个字节的m / 2个字节的页面大小和n / 2个数据端子DQ。 第二存储器架构具有p个存储体，页面大小为m字节和n个数据终端。 选项过程可以通过粘合，掩模图案或保险丝来实现。 在存储器设备中，页面大小和存储体数量由设计选项进行调整。 因此，存储器架构被修改，冗余灵活性增加并且功耗降低。

公开(公告)号：US6163498A

公开(公告)日：2000-12-19

申请号：US396144

申请日：1999-09-15

申请人： Byung-sick Moon

发明人： Byung-sick Moon

IPC分类号： G11C11/407 ,  G11C8/00 ,  G11C8/06

CPC分类号： G11C8/00 ,  G11C8/06

摘要： An integrated circuit device is provided having a column selection circuit which activates the column selection line output responsive to a column latch signal rather than a data command signal. The leading edge of the column latch signal is used to generate a master clock signal and to latch the selected address. The master clock signal is delayed and a column decoder circuit decodes the latched selected address to activate the appropriate column selection line output responsive to the delayed clock. As activation of the column selection line output initiates placement of the desired sense amplified bit line signal on the local input and output lines, the voltage differential on the local input and output lines can begin to develop earlier than with the prior art approaches. Therefore, the voltage levels on the local input and output lines may reach the desired levels before or shortly after the data command signal is activated thereby allowing the input and output sense amplifier to be enabled and output the read data shortly after the data command signal is activated. Write operations may be similarly supported. Methods are also provided.

摘要翻译： 提供一种具有列选择电路的集成电路装置，其响应于列锁存信号而不是数据命令信号来激活列选择线输出。 列锁存信号的前沿用于产生主时钟信号并锁存所选择的地址。 主时钟信号被延迟，并且列解码器电路对锁存的所选地址进行解码，以响应于延迟的时钟激活适当的列选择线输出。 随着列选择线输出的激活启动所需感测放大位线信号在本地输入和输出线路上的放置，本地输入和输出线路上的电压差可以比现有技术方法更早地开始发展。 因此，本地输入和输出线路上的电压电平可以在数据命令信号被激活之前或不久之后达到期望的水平，从而允许输入和输出读出放大器被使能，并且在数据命令信号为 活性。 可以类似地支持写操作。 还提供了方法。

公开(公告)号：US6078536A

公开(公告)日：2000-06-20

申请号：US207534

申请日：1998-12-08

申请人： Byung-sick Moon ,  Kye-hyun Kyung ,  Sung-joo Lee

发明人： Byung-sick Moon ,  Kye-hyun Kyung ,  Sung-joo Lee

IPC分类号： G11C11/34 ,  G11C5/06 ,  G11C11/401 ,  G11C29/12 ,  G11C29/48 ,  G11C7/00

CPC分类号： G11C29/48 ,  G11C5/066

摘要： An integrated circuit memory device and method including a direct mode assigns internal data and address signals to separate pins. In particular, a plurality of first pins is assigned to the plurality of internal data signals that provide the data to the memory array in direct test mode. A plurality of second pins is assigned to the plurality of internal address signals that provide the address to the memory array in direct test mode, wherein none of the pins included in first plurality of pins are included in the second plurality of pins.

摘要翻译： 包括直接模式的集成电路存储器件和方法将内部数据和地址信号分配给单独的引脚。 特别地，将多个第一引脚分配给在直接测试模式下将数据提供给存储器阵列的多个内部数据信号。 多个第二引脚被分配给在直接测试模式下向存储器阵列提供地址的多个内部地址信号，其中包括在第一多个引脚中的引脚都不包括在第二多个引脚中。