利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

49 条记录 (耗时 0.024 秒)

    Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
    1.
    发明授权
    Method to avoid copper contamination on the sidewall of a via or a dual damascene structure 有权
    避免在通孔或双镶嵌结构的侧壁上铜污染的方法

    公开(公告)号：US6114243A

    公开(公告)日：2000-09-05

    申请号：US439361

    申请日：1999-11-15

    申请人： Subhash Gupta ,  Kwok Keung Paul Ho ,  Mei-Sheng Zhou ,  Simon Chool

    发明人： Subhash Gupta ,  Kwok Keung Paul Ho ,  Mei-Sheng Zhou ,  Simon Chool

    IPC分类号： H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76877

    摘要： A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.

    摘要翻译： 描述了在通过或双镶嵌蚀刻期间通过在第一铜金属化上形成覆盖层来防止金属间电介质层的铜污染的新方法。 第一铜金属化形成在覆盖半导体衬底的电介质层中，其中阻挡金属层形成在第一铜金属化层下方并且覆盖在电介质层上。 第一铜金属化被平坦化，然后被蚀刻以在介电层的表面下方形成凹陷。 导电覆盖层沉积在凹槽内的第一铜金属化层上并覆盖在介电层上。 使用几种方法之一除去在凹槽内的第一铜金属化之外除去导电覆盖层。 覆盖介电层和覆盖第一铜金属化的导电覆盖层的金属间电介质层被沉积。 通孔或双镶嵌开口通过金属间电介质层被蚀刻到导电覆盖层，其中导电覆盖层防止蚀刻期间金属间介电层的铜污染。 通孔或双镶嵌开口填充有金属层，以在集成电路器件的制造中完成电连接。

    Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects
    2.
    发明授权
    Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects 失效
    将富硅材料集成在双镶嵌互连的自对准通孔中

    公开(公告)号：US06350675B1

    公开(公告)日：2002-02-26

    申请号：US09686282

    申请日：2000-10-12

    申请人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

    发明人： Simon Chooi ,  Mei-Sheng Zhou ,  Subhash Gupta ,  Yi Xu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76832 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826

    摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.

    摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及形成自对准的双镶嵌互连和通孔，其结合了低介电常数金属间电介质（IMD）并利用甲硅烷基化的顶表面成像（TSI ）光致抗蚀剂，具有单步或多步选择性反应离子蚀刻（RIE）工艺，以形成沟槽/通孔。 本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像（TSI）抗蚀剂蚀刻阻挡层以形成通孔图案。 在本发明的第一和第二实施例中描述了使用顶表面成像（TSI）抗蚀剂的两种变型，其具有和不具有将暴露区域保持在适当位置，此外，使用刚好低于 抗蚀剂层。 提供顶表面成像（TSI）光致抗蚀剂和低介电常数金属间电介质（IMD）之间的粘附性是好的，可以省略上述薄介电层，产生本发明的第三和第四实施例。 该方法中特别注意保护低介电常数金属间电介质（ILD）材料的完整性，该材料选自有机基或掺碳二氧化硅。

    Reversed damascene process for multiple level metal interconnects
    4.
    发明授权
    Reversed damascene process for multiple level metal interconnects 有权
    用于多级金属互连的反向镶嵌工艺

    公开(公告)号：US06352917B1

    公开(公告)日：2002-03-05

    申请号：US09598691

    申请日：2000-06-21

    申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    IPC分类号： H01L214763

    CPC分类号： H01L21/76885 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.

    摘要翻译： 已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。 该方法创建一个反向的双镶嵌结构。 第一电介质层设置在半导体衬底上。 图案化电介质层以形成用于计划的大马士革互连的沟槽。 可以可选地在沟槽侧壁上形成绝缘间隔物。 导电阻挡层沉积在电介质层上并衬在沟槽上。 沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。 金属层和导电阻挡层被抛光，从而形成镶嵌互连。 可以任选地沉积钝化层。 大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。 图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。 在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

    Selective etching of unreacted nickel after salicidation
    5.
    发明授权
    Selective etching of unreacted nickel after salicidation 有权
    腐蚀后对未反应的镍进行选择性蚀刻

    公开(公告)号：US06225202B1

    公开(公告)日：2001-05-01

    申请号：US09598689

    申请日：2000-06-21

    申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

    IPC分类号： H01L214763

    CPC分类号： H01L29/665 ,  C23F4/00 ,  H01L21/32136

    摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.

    摘要翻译： 描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。 在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。 在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。 在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。 半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。 将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

    Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
    8.
    发明授权
    Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene 有权
    复合硅 - 金属氮化物屏障，以防铜铜镶嵌中金属氟化物的形成

    公开(公告)号：US06372636B1

    公开(公告)日：2002-04-16

    申请号：US09587467

    申请日：2000-06-05

    申请人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

    发明人： Simon Chooi ,  Subhash Gupta ,  Mei-Sheng Zhou ,  Sangki Hong

    IPC分类号： H01L214763

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76855

    摘要： A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure -single, dual, or multi-structure- is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer. In the third embodiment, the ternary metal silicon nitride spacer is formed by etching after having first formed the amorphous silicon layer and the nitride layer, in that order, and then etching the passivation/barrier layer at the bottom of the damascene structure into the underlying copper layer. In all three embodiments, metal nitride reacts with amorphous silicon to form a ternary metal silicon nitride having an excellent property of adhering to copper while at the same time for forming an excellent barrier to diffusion of copper.

    摘要翻译： 公开了一种形成非晶硅间隔物的方法，随后在铜镶嵌结构 - 单，双或多结构中在间隔物上形成金属氮化物，以防止在铜中形成氟化物。 在第一实施例中，通过在形成在内部的非晶硅间隔物上形成金属氮化物层之后，通过从双镶嵌结构形成开口到下面的铜层来形成铜镶嵌层和下面的铜金属层之间的互连 双镶嵌结构的墙壁。 在第二实施例中，通过在形成非晶硅间隔物之后并且在形成金属氮化物层之前通过蚀刻到下面的铜层中，由双镶嵌结构制造双镶嵌结构和下面的铜线之间的互连。 在第三实施例中，三元金属氮化硅间隔物依次先形成非晶硅层和氮化物层后，通过蚀刻形成，然后在镶嵌结构的底部蚀刻钝化/阻挡层，形成底层 铜层。 在所有三个实施例中，金属氮化物与非晶硅反应形成具有优异的粘附铜特性的三元金属氮化硅，同时形成对铜的扩散的优异屏障。