公开(公告)号：US07133304B2

公开(公告)日：2006-11-07

申请号：US10805809

申请日：2004-03-22

申请人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  Hugh P. McAdams ,  Anand Seshadri ,  Jarrod Eliason

发明人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  Hugh P. McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

摘要翻译： 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US07301795B2

公开(公告)日：2007-11-27

申请号：US11260987

申请日：2005-10-28

申请人： John Y. Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Kumar Madan ,  Jarrod Eliason

发明人： John Y. Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Kumar Madan ,  Jarrod Eliason

IPC分类号： G11C11/22

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

公开(公告)号：US20080084773A1

公开(公告)日：2008-04-10

申请号：US11543338

申请日：2006-10-04

申请人： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

发明人： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

摘要： One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

摘要翻译： 本发明的一个方面涉及一种用于访问存储器件的方法。 一个实施例涉及访问存储器件的方法。 在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。 在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。 还公开了其它系统和方法。

公开(公告)号：US07630257B2

公开(公告)日：2009-12-08

申请号：US11543338

申请日：2006-10-04

申请人： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

发明人： Sudhir Kumar Madan ,  Hugh P. Mcadams ,  Sung-Wei Lin

IPC分类号： G11C7/00

CPC分类号： G11C11/22 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

摘要： One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.

摘要翻译： 本发明的一个方面涉及一种用于访问存储器件的方法。 一个实施例涉及访问存储器件的方法。 在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。 在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。 还公开了其它系统和方法。

公开(公告)号：US07200027B2

公开(公告)日：2007-04-03

申请号：US11100013

申请日：2005-04-06

申请人： Anand Seshadri ,  Jarrod R. Eliason ,  Sudhir Kumar Madan

发明人： Anand Seshadri ,  Jarrod R. Eliason ,  Sudhir Kumar Madan

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column. The first switching device (S1) couples the staging capacitance (Cs) to the precharged primary capacitance (130) and then isolates the precharged staging capacitance (Cs) from the primary capacitance (130), and the second switching device (S2, S3) isolates the staging capacitance (Cs) from the bitline while the staging capacitance Cs is coupled to the primary capacitance (130), and then couples the precharged staging capacitance (Cs) to the bitline to provide a reference voltage to the bitline during the memory access operation.

摘要翻译： 参考发生器系统（108,130）和方法（200）被提供用于为铁电存储器件（102）中的存储器存取操作提供位线参考电压。 参考发生器系统（108,130）包括初级电容（130），对初级电容充电的预充电系统（132）以及具有多个与相应的电压相关联的多个局部参考电路（108a）的参考系统（108） 单独地包括分级电容（Cs）的阵列列，耦合在所述分级电容和所述初级电容（130）之间的第一开关器件（S1）以及耦合在所述分级电容之间的第二开关器件（S 2，S 3） （Cs）和相应阵列列的位线。 第一开关器件（S1）将分级电容（Cs）耦合到预充电的初级电容（130），然后将预充电的分级电容（Cs）与主电容（130）隔离，并且第二开关器件（S2， S 3）将分级电容（Cs）与位线分离，而分级电容Cs耦合到初级电容（130），然后将预充电分级电容（Cs）耦合到位线，以在位线期间向位线提供参考电压 内存访问操作。

公开(公告)号：US07443708B2

公开(公告)日：2008-10-28

申请号：US11409628

申请日：2006-04-24

申请人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  John Fong

发明人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  John Fong

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  H01L27/11502

摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US20080151598A1

公开(公告)日：2008-06-26

申请号：US11756466

申请日：2007-05-31

申请人： Sudhir Kumar Madan

发明人： Sudhir Kumar Madan

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Memory devices are provided, having a ferroelectric memory array and a zero cancellation system with one or more zero cancellation circuits for coupling a negative charge to a memory array bitline through a zero cancellation capacitor while a memory cell plateline signal is applied during a read operation, wherein one or more layers of the zero cancellation system layout is identical or substantially identical to that of the memory cells of the array.

摘要翻译： 提供存储器件，其具有铁电存储器阵列和具有一个或多个零消除电路的零消除系统，用于通过零消除电容器将负电荷耦合到存储器阵列位线，同时在读取操作期间施加存储器单元平面信号， 其中零消除系统布局的一个或多个层与阵列的存储器单元的一个或多个层相同或基本相同。

公开(公告)号：US20080144351A1

公开(公告)日：2008-06-19

申请号：US11954371

申请日：2007-12-12

申请人： Jarrod Randall Eliason ,  Sudhir Kumar Madan

发明人： Jarrod Randall Eliason ,  Sudhir Kumar Madan

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： One embodiment relates to a method for accessing ferroelectric memory cells in a ferroelectric memory device. A first memory access is performed on the cell, and a second memory access is performed on the cell. An approximately same bias is applied to the bitline and plateline of the cell for a time between the first memory access and the second memory access. Other methods and systems are also disclosed.

摘要翻译： 一个实施例涉及在铁电存储器件中访问铁电存储器单元的方法。 在小区上执行第一存储器访问，并且在该单元上执行第二存储器访问。 在第一存储器访问和第二存储器访问之间的时间内，大致相同的偏差被施加到单元的位线和平行线。 还公开了其它方法和系统。

公开(公告)号：US07193880B2

公开(公告)日：2007-03-20

申请号：US10866834

申请日：2004-06-14

申请人： Sudhir Kumar Madan ,  John Fong

发明人： Sudhir Kumar Madan ,  John Fong

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells (106) during memory access operations to mitigate cell storage node disturbances.

摘要翻译： 提出了方法（50,70）和铁电装置（102），其中脉冲（113）在存储器访问操作期间被选择性地施加到一个或多个未选择的铁电存储器单元（106）的板条（PL），以减轻电池存储 节点干扰。

公开(公告)号：US07561458B2

公开(公告)日：2009-07-14

申请号：US11756466

申请日：2007-05-31

申请人： Sudhir Kumar Madan

发明人： Sudhir Kumar Madan

IPC分类号： G11C11/34

CPC分类号： G11C11/22

摘要： Memory devices are provided, having a ferroelectric memory array and a zero cancellation system with one or more zero cancellation circuits for coupling a negative charge to a memory array bitline through a zero cancellation capacitor while a memory cell plateline signal is applied during a read operation, wherein one or more layers of the zero cancellation system layout is identical or substantially identical to that of the memory cells of the array.

摘要翻译： 提供存储器件，其具有铁电存储器阵列和具有一个或多个零消除电路的零消除系统，用于通过零消除电容器将负电荷耦合到存储器阵列位线，同时在读取操作期间施加存储器单元平面信号， 其中零消除系统布局的一个或多个层与阵列的存储器单元的一个或多个层相同或基本相同。