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    Low resistance plate line bus architecture
    1.
    发明授权
    Low resistance plate line bus architecture 有权
    低电阻板线总线架构

    公开(公告)号：US07443708B2

    公开(公告)日：2008-10-28

    申请号：US11409628

    申请日：2006-04-24

    申请人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  John Fong

    发明人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  John Fong

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  H01L27/11502

    摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

    摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

    Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory
    2.
    发明授权
    Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory 有权
    扁平电压脉冲以减少铁电存储器中的存储节点干扰

    公开(公告)号：US07193880B2

    公开(公告)日：2007-03-20

    申请号：US10866834

    申请日：2004-06-14

    申请人： Sudhir Kumar Madan ,  John Fong

    发明人： Sudhir Kumar Madan ,  John Fong

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells (106) during memory access operations to mitigate cell storage node disturbances.

    摘要翻译： 提出了方法（50,70）和铁电装置（102），其中脉冲（113）在存储器访问操作期间被选择性地施加到一个或多个未选择的铁电存储器单元（106）的板条（PL），以减轻电池存储 节点干扰。

    Plateline driver with RAMP rate control
    3.
    发明授权
    Plateline driver with RAMP rate control 有权
    具有RAMP速率控制的Plateline驱动程序

    公开(公告)号：US07349237B2

    公开(公告)日：2008-03-25

    申请号：US11003707

    申请日：2004-12-03

    申请人： Sung-Wei Lin ,  Sudhir K. Madan ,  John Fong

    发明人： Sung-Wei Lin ,  Sudhir K. Madan ,  John Fong

    IPC分类号： G11C11/00 ,  G11C5/14

    CPC分类号： H03K19/00346 ,  H03K19/185

    摘要： A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). A first conductor (710, 850) is coupled to a plurality of the rows (702, 704, and 706) of memory cells. A first transistor (810) has a current path coupled between a voltage supply terminal (800) and the first conductor (850) and a control terminal coupled to receive a first control signal (PLV). A second transistor (820) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

    摘要翻译： 公开了一种减少字线耦合的存储电路和方法。 电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。 第一导体（710,850）耦合到存储器单元的多个行（702,704和706）。 第一晶体管（810）具有耦合在电压源端子（800）和第一导体（850）之间的电流通路和耦合以接收第一控制信号（PLV）的控制端子。 第二晶体管（820）具有耦合在电压供应端和第一导体之间的电流路径，以及耦合以接收第二控制信号（PLW）的控制端。

    Accelerated low power fatigue testing of fram
    4.
    发明申请
    Accelerated low power fatigue testing of fram 有权
    框架加速低功率疲劳试验

    公开(公告)号：US20060107095A1

    公开(公告)日：2006-05-18

    申请号：US11260987

    申请日：2005-10-28

    申请人： John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

    发明人： John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

    IPC分类号： G06F11/00

    CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

    摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

    摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

    Photocurable compositions containing reactive particles
    5.
    发明申请
    Photocurable compositions containing reactive particles 有权
    含有反应性颗粒的光固化组合物

    公开(公告)号：US20050175925A1

    公开(公告)日：2005-08-11

    申请号：US10511924

    申请日：2003-04-18

    申请人： David Johnson ,  John Fong

    发明人： David Johnson ,  John Fong

    IPC分类号： G03F7/027 ,  C08F2/46 ,  G03F7/00 ,  G03F7/004 ,  G03F7/029 ,  G03F7/032 ,  G03F7/033 ,  G03F7/038 ,  G03F7/075 ,  G03F7/26 ,  G03F7/40 ,  H05K1/00 ,  H05K3/28

    CPC分类号： H05K3/28 ,  B33Y10/00 ,  B33Y70/00 ,  G03F7/0037 ,  G03F7/032 ,  G03F7/0388 ,  G03F7/0757 ,  H05K3/0023 ,  H05K3/287 ,  H05K3/4676 ,  H05K2203/1476 ,  Y10T428/31909

    摘要： A photocurable composition, including (a) a photocurable monomer, e.g. a cationically curable monomer and/or a radically curable monomer; (b) reactive particles comprising a crosslinked elastomeric core, e.g. made of polysiloxane material, and a shell of reactive groups on an outer surface of the core, wherein the reactive groups comprise epoxy groups, ethylenically unsaturated groups, or hydroxy groups; and (c) an appropriate photoinitiator, e.g. a radical photoinitiator; and a cationic photoinitiator. A method of making a 3-D object from such a composition and a 3-D object made by the method are also provided. The cured composition generally has a smooth surface. The use of the reactive particles makes the composition more stable and the particles do not readily separate out.

    摘要翻译： 光固化性组合物，包括（a）光固化性单体， 阳离子可固化单体和/或可自由基固化的单体; （b）包含交联的弹性体芯的反应性颗粒，例如 由聚硅氧烷材料制成，并且在芯的外表面上具有反应性基团的壳，其中反应性基团包括环氧基，烯键式不饱和基团或羟基; 和（c）适当的光引发剂，例如 激光光引发剂; 和阳离子光引发剂。 还提供了由这种组合物制成3-D物体的方法和通过该方法制造的3-D物体。 固化的组合物通常具有光滑的表面。 使用反应性颗粒使得组合物更稳定，并且颗粒不容易分离出来。

    PHOTOCURABLE COMPOSITIONS CONTAINING REACTIVE POLYSILOXANE PARTICLES
    6.
    发明申请
    PHOTOCURABLE COMPOSITIONS CONTAINING REACTIVE POLYSILOXANE PARTICLES 有权
    含有反应性聚硅氧烷颗粒的光致抗蚀剂组合物

    公开(公告)号：US20080057217A1

    公开(公告)日：2008-03-06

    申请号：US11931131

    申请日：2007-10-31

    申请人： David Johnson ,  John Fong

    发明人： David Johnson ,  John Fong

    IPC分类号： B05D3/06 ,  C08F2/46

    CPC分类号： H05K3/28 ,  B33Y10/00 ,  B33Y70/00 ,  G03F7/0037 ,  G03F7/032 ,  G03F7/0388 ,  G03F7/0757 ,  H05K3/0023 ,  H05K3/287 ,  H05K3/4676 ,  H05K2203/1476 ,  Y10T428/31909

    摘要： A photocurable composition, including (a) a cationically curable monomer; (b) a radically curable monomer; (c) reactive particles comprising a crosslinked polysiloxane core and a shell of reactive groups on an outer surface of the core, wherein the reactive groups comprise epoxy groups, ethylenically unsaturated groups, or hydroxy groups; (d) a radical photoinitiator; and (e) a cationic photoinitiator. A method of making a 3-D object from such a composition. A 3-D object made by the method.

    摘要翻译： 一种光固化性组合物，其包含（a）阳离子固化性单体; （b）可自由基固化的单体; （c）反应性颗粒包含交联聚硅氧烷核心和核心外表面上的反应性基团壳，其中反应性基团包括环氧基，烯属不饱和基团或羟基; （d）自由基光引发剂; 和（e）阳离子光引发剂。 从这种组合物制备3-D物体的方法。 由该方法制作的3-D物体。

    Set associative repair cache systems and methods
    7.
    发明申请
    Set associative repair cache systems and methods 审中-公开
    设置关联修复缓存系统和方法

    公开(公告)号：US20060080572A1

    公开(公告)日：2006-04-13

    申请号：US11231001

    申请日：2005-09-20

    申请人： John Fong

    发明人： John Fong

    IPC分类号： G06F11/00

    CPC分类号： G11C29/808

    摘要： The present invention facilitates scaling of memory devices and operation thereof by employing a set associative repair cache system to correct or repair identified faulty memory cells. A repair cache region router 602 compares a repair region portion of a memory address to repair cache regions to identify a matching repair cache region. Then, a local repair location router 603 compares a repair address portion of the memory address to a local repair location addresses particular to the matching repair cache region to identify a matching local repair address. If a matching local repair address is identified, a repair component 606 provides access to a repair data location according to the matching local repair address and the matching repair cache region. Otherwise, a main memory 604 provides access to a memory location according to the memory address. Other systems and methods are disclosed.

    摘要翻译： 本发明通过采用一组关联修复缓存系统来校正或修复所识别的故障存储器单元，便于存储器件的缩放及其操作。 修复高速缓存区域路由器602将存储器地址的修复区域部分与修复高速缓存区域进行比较，以识别匹配的修复高速缓存区域。 然后，本地修复位置路由器603将存储器地址的修复地址部分与匹配修复高速缓存区域特定的本地修复位置地址进行比较，以识别匹配的本地修复地址。 如果识别出匹配的本地修复地址，则修复组件606根据匹配的本地修复地址和匹配修复高速缓存区域提供对修复数据位置的访问。 否则，主存储器604根据存储器地址提供对存储器位置的访问。 公开了其它系统和方法。

    Low resistance plate line bus architecture
    10.
    发明申请
    Low resistance plate line bus architecture 有权
    低电阻板线总线架构

    公开(公告)号：US20070211510A1

    公开(公告)日：2007-09-13

    申请号：US11409628

    申请日：2006-04-24

    申请人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

    发明人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

    IPC分类号： G11C11/22 ,  G11C5/06 ,  G11C11/42

    CPC分类号： G11C11/22 ,  H01L27/11502

    摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

    摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。