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1.发明授权Method and apparatus to reduce storage node disturbance in ferroelectric memory 有权减少铁电存储器节点干扰的方法和装置公开(公告)号：US07133304B2
公开(公告)日：2006-11-07
申请号：US10805809
申请日：2004-03-22
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
摘要翻译： 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。
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公开(公告)号：US07301795B2
公开(公告)日：2007-11-27
申请号：US11260987
申请日：2005-10-28
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。
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公开(公告)号：US20080084773A1
公开(公告)日：2008-04-10
申请号：US11543338
申请日：2006-10-04
CPC分类号： G11C11/22 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.
摘要翻译： 本发明的一个方面涉及一种用于访问存储器件的方法。 一个实施例涉及访问存储器件的方法。 在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。 在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。 还公开了其它系统和方法。
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公开(公告)号：US07630257B2
公开(公告)日：2009-12-08
申请号：US11543338
申请日：2006-10-04
IPC分类号： G11C7/00
CPC分类号： G11C11/22 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： One aspect of the invention relates to a method for accessing a memory device. One embodiment relates to a method for accessing a memory device. In the method during a read operation, one data value is provided on a local IO line while complimentary local IO line that is associated with the local IO line is inactivated. During a write operation, another data value is provided on the local IO line and a complimentary data value is provided on the complimentary local IO line. Other systems and methods are also disclosed.
摘要翻译： 本发明的一个方面涉及一种用于访问存储器件的方法。 一个实施例涉及访问存储器件的方法。 在读操作期间的方法中，在本地IO线上提供一个数据值，而与本地IO线相关联的互补本地IO线被停用。 在写操作期间，本地IO线上提供另一个数据值，并在互补的本地IO线上提供补充数据值。 还公开了其它系统和方法。
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5.发明申请Method and apparatus to reduce storage node disturbance in ferroelectric memory 有权减少铁电存储器节点干扰的方法和装置公开(公告)号：US20050207201A1
公开(公告)日：2005-09-22
申请号：US10805809
申请日：2004-03-22
申请人： Sudhir Madan , Sung-Wei Lin , Hugh McAdams , Anand Seshadri , Jarrod Eliason
发明人： Sudhir Madan , Sung-Wei Lin , Hugh McAdams , Anand Seshadri , Jarrod Eliason
CPC分类号： G11C11/22
摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
摘要翻译： 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。
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公开(公告)号：US20060107095A1
公开(公告)日：2006-05-18
申请号：US11260987
申请日：2005-10-28
申请人： John Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Madan , Jarrod Eliason
发明人： John Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Madan , Jarrod Eliason
IPC分类号： G06F11/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。
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公开(公告)号：US07443708B2
公开(公告)日：2008-10-28
申请号：US11409628
申请日：2006-04-24
申请人： Sudhir Kumar Madan , Sung-Wei Lin , John Fong
发明人： Sudhir Kumar Madan , Sung-Wei Lin , John Fong
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , H01L27/11502
摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.
摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。
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公开(公告)号：US20070038805A1
公开(公告)日：2007-02-15
申请号：US11200390
申请日：2005-08-09
申请人： Jarrod Eliason , Sudhir Madan , Sung-Wei Lin , Hugh McAdams
发明人： Jarrod Eliason , Sudhir Madan , Sung-Wei Lin , Hugh McAdams
IPC分类号： G06F12/00
CPC分类号： G11C29/848 , G11C11/22 , G11C29/816
摘要： A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.
摘要翻译： 公开了处理或处理有缺陷的“晶粒”或非易失性铁电存储器阵列的部分的方案。 在一个示例中，存储器的颗粒小于高和小于行宽的列。 当修复编程组发现部分的地址对应于失败的行地址和故障列地址时，对存储器部分执行替换操作。
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公开(公告)号：US07463504B2
公开(公告)日：2008-12-09
申请号：US11227936
申请日：2005-09-15
申请人： Sung-Wei Lin , Sudhir Madan
发明人： Sung-Wei Lin , Sudhir Madan
IPC分类号： G11C11/22
摘要： Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line. The method may further optionally comprise grounding the dummy bit line after pulsing the plate line, and optionally disabling the word line after grounding the dummy bit line to precondition the cell for the next memory operation.
摘要翻译： 描述了用于以避免在存储器阵列的边缘处沿着虚拟位线的存储器单元中的栅极氧化物的过压击穿的方式来操作FeRAM和其它这样的存储器件的方法，所述方法包括在板期间浮置虚拟位线 线脉冲活动。 在本发明的一个实施方式中，该方法被应用于具有板线，伪位线，传输晶体管和铁电存储电容器的FeRAM虚拟单元。 该方法包括首先将虚拟位线接地作为优选的前提条件，然而，如果存储电容器的存储节点以其他方式接地，则该步骤可以被认为是可选步骤。 该方法然后包括浮置虚拟位线，激活与存储器单元相关联的字线，以及脉冲板线。 或者，该方法包括将代替虚拟位线或浮置虚拟位线之前的正电压偏压施加到虚拟位线。 该方法可以进一步可选地包括在脉冲板线之后对虚拟位线进行接地，并且可选地在使虚拟位线接地之后禁用字线，以对单元进行下一个存储器操作的预处理。
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公开(公告)号：US5657268A
公开(公告)日：1997-08-12
申请号：US560670
申请日：1995-11-20
申请人： Phat C. Truong , Sung-Wei Lin
发明人： Phat C. Truong , Sung-Wei Lin
摘要： In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate coupled to a wordline and each memory cell of a row in another sector has a control gate coupled to that wordline, a method for programming a memory cell in one sector of said method includes connecting at least the second common array-source line to each bitline coupled to drains of columns of memory cells in the another sector, then biasing at a positive voltage both the common array-source line and the bitlines coupled to drains of memory cells in columns of the another sector, and then applying a programming voltage to the selected wordline coupled to the control gate of the selected cell in the first sector. An erasing method includes connecting the wordlines to a reference voltage, connecting at least one deselected common array-source line to each bitline coupled to drains of columns of memory cells in the deselected sector, then biasing at a positive voltage both the deselected common array-source line and said bitlines coupled to drains of memory cells in columns of the deselected sector, and then applying a positive erasing voltage to said common array-source line of the selected sector.
摘要翻译： 在其中每个存储器单元具有耦合到位线的漏极的多扇区非易失性存储器阵列中，每个扇区的每个存储单元具有耦合到公共阵列源极线的源极，第一扇区的一行中的每个存储器单元具有 耦合到字线的控制栅极和另一扇区中的行的每个存储器单元具有耦合到该字线的控制栅极，用于对所述方法的一个扇区中的存储器单元进行编程的方法包括至少连接第二公共数组源极线 耦合到另一扇区中的存储器单元列的排列的每个位线，然后以正电压偏置公共阵列源极线和与另一扇区的列中的存储器单元的漏极耦合的位线，然后施加编程 电压被连接到第一扇区中所选择的单元的控制栅极的选定字线。 擦除方法包括将字线连接到参考电压，将至少一个未选择的公共阵列源线连接到耦合到取消选择的扇区中的存储器单元的列的排列的每个位线，然后以正电压偏置所选择的公共阵列 - 源极线和所述位线耦合到取消选择的扇区的列中的存储器单元的漏极，然后将正的擦除电压施加到所选择的扇区的所述公共阵列源极线。
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