利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.025 秒)

    Non-volatile memory device and method of fabricating the same
    1.
    发明申请
    Non-volatile memory device and method of fabricating the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20090321815A1

    公开(公告)日：2009-12-31

    申请号：US12453035

    申请日：2009-04-28

    申请人： Suk-kang Sung ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur

    发明人： Suk-kang Sung ,  Jung-dal Choi ,  Choong-ho Lee ,  Sung-hoi Hur

    IPC分类号： H01L29/792 ,  H01L27/092

    CPC分类号： H01L21/823493 ,  H01L21/823456 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/792

    摘要： A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.

    摘要翻译： 一种非易失性存储器件，包括第一导电类型的衬底，所述衬底包括多个第二导电类型的阱，多个第二导电类型的阱之一中的多个存储单元，以及周边 包括至少一个第一导电类型的第一晶体管和第二导电类型的另一个第二导电类型的第二导体类型的第二晶体管。

    Methods of Manufacturing Semiconductor devices Having Buried Bit Lines
    2.
    发明申请
    Methods of Manufacturing Semiconductor devices Having Buried Bit Lines 审中-公开
    制造埋置位线的半导体器件的方法

    公开(公告)号：US20070190725A1

    公开(公告)日：2007-08-16

    申请号：US11740525

    申请日：2007-04-26

    申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

    摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines
    3.
    发明申请
    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
    具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法

    公开(公告)号：US20060131613A1

    公开(公告)日：2006-06-22

    申请号：US11240544

    申请日：2005-09-30

    申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    IPC分类号： H01L27/10

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

    摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines
    4.
    发明授权
    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
    具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法

    公开(公告)号：US07227220B2

    公开(公告)日：2007-06-05

    申请号：US11240544

    申请日：2005-09-30

    申请人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    发明人： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

    摘要翻译： 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

    Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same
    5.
    发明授权
    Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same 有权
    多位多级非易失性存储器件及其操作和制造方法

    公开(公告)号：US07602010B2

    公开(公告)日：2009-10-13

    申请号：US11407133

    申请日：2006-04-19

    申请人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

    发明人： Byung-yong Choi ,  Tae-yong Kim ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho ,  Dong-gun Park ,  Choong-ho Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851

    摘要： In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.

    摘要翻译： 在允许多位和/或多电平操作的非易失性存储器件及其操作和制造方法中，非易失性存储器件在一个实施例中包括：半导体衬底，掺杂有第一 导电型，其具有由形成在基板中的至少两个分开的沟槽限定的一个或多个散热片，散热片沿第一方向沿着基板延伸; 成对的栅电极在散热片的侧壁处形成为间隔物，其中栅电极与包括散热片的半导体基板绝缘，并平行于翅片延伸; 栅电极和鳍之间的存储节点，并与栅电极和半导体衬底绝缘; 源极区域和漏极区域，其掺杂有第二导电类型的杂质，并且分别形成在鳍片的至少在表面部分并且延伸穿过翅片的第一方向; 以及对应于各个栅电极的沟道区，至少在源极和漏极区之间的翅片的侧壁的表面区域处形成。

    METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES USING INCLINED ION IMPLANTATION
    8.
    发明申请
    METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES USING INCLINED ION IMPLANTATION 审中-公开
    使用离子植入法制造非易失性记忆体装置的方法

    公开(公告)号：US20100317169A1

    公开(公告)日：2010-12-16

    申请号：US12708030

    申请日：2010-02-18

    申请人： Suk-kang Sung ,  Keon-soo Kim ,  Min-chul Kim ,  Se-jun Park

    发明人： Suk-kang Sung ,  Keon-soo Kim ,  Min-chul Kim ,  Se-jun Park

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11529 ,  H01L21/26586 ,  H01L21/823425 ,  H01L27/11526 ,  H01L29/66825

    摘要： Provided is a method of manufacturing a non-volatile memory device by performing ion implantation at an angle such that active regions of memory cell transistors in a cell region and peripheral transistors in a peripheral region each have different doping concentrations. The method includes forming a plurality of memory cell transistor gates on a cell region of a substrate surface and a plurality of peripheral transistor gates on a peripheral region of the substrate surface, where a distance between adjacent ones of the peripheral transistor gates is greater than a distance between adjacent ones of the memory cell transistor gates, and performing an ion implantation process at an implantation angle that is selected based on a height of the memory cell transistor gates and the distance between the adjacent ones thereof to implant ions into portions of the peripheral region between the peripheral transistor gates without implanting the ions into portions of the cell region between the memory cell transistor gates.

    摘要翻译： 提供了通过以使得单元区域中的存储单元晶体管的有源区域和周边区域中的外围晶体管的各自具有不同的掺杂浓度的角度进行离子注入来制造非易失性存储器件的方法。 该方法包括在衬底表面的单元区域上形成多个存储单元晶体管栅极和在衬底表面的周边区域上的多个外围晶体管栅极，其中相邻的周边晶体管栅极之间的距离大于 并且以基于存储单元晶体管栅极的高度和其相邻距离之间的距离选择的注入角度进行离子注入工艺，以将离子注入到外围部分中 外围晶体管栅极之间的区域，而不将离子注入存储单元晶体管栅极之间的单元区域的部分。