公开(公告)号：US20230207551A1

公开(公告)日：2023-06-29

申请号：US17561693

申请日：2021-12-23

申请人： Sukru YEMENICIOGLU ,  Richard E. SCHENKER ,  Xinning WANG ,  Mauro J. KOBRINSKY ,  Tahir GHANI

发明人： Sukru YEMENICIOGLU ,  Richard E. SCHENKER ,  Xinning WANG ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC分类号： H01L27/02 ,  H01L23/522 ,  G06F30/394

CPC分类号： H01L27/0207 ,  H01L23/5226 ,  G06F30/394

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. Other embodiments may be described or claimed.

公开(公告)号：US20230187444A1

公开(公告)日：2023-06-15

申请号：US17549530

申请日：2021-12-13

申请人： Sukru YEMENICIOGLU ,  Xinning WANG ,  Allen B. GARDINER ,  Tahir GHANI ,  Mohit K. HARAN ,  Leonard P. GULER

发明人： Sukru YEMENICIOGLU ,  Xinning WANG ,  Allen B. GARDINER ,  Tahir GHANI ,  Mohit K. HARAN ,  Leonard P. GULER

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

摘要： Integrated circuit structures having gate cut offset, and methods of fabricating integrated circuit structures having gate cut offset, are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion, the gate cut laterally closer to the second vertical stack of horizontal nanowires than to the first vertical stack of horizontal nanowires.

公开(公告)号：US20230187515A1

公开(公告)日：2023-06-15

申请号：US17549550

申请日：2021-12-13

申请人： Sukru YEMENICIOGLU ,  Tahir GHANI ,  Xinning WANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  Mohit K. HARAN

发明人： Sukru YEMENICIOGLU ,  Tahir GHANI ,  Xinning WANG ,  Leonard P. GULER ,  Charles H. WALLACE ,  Mohit K. HARAN

IPC分类号： H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/78696

摘要： Described herein are integrated circuit structures having versatile channel placement, and methods of fabricating integrated circuit structures having versatile channel placement. In an example, an integrated circuit structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is immediately neighboring and parallel with the first vertical stack of horizontal nanowires and has a second width greater than the first width. A third vertical stack of horizontal nanowires is immediately neighboring and parallel with the second vertical stack of horizontal nanowires and has the first width.

公开(公告)号：US20230197609A1

公开(公告)日：2023-06-22

申请号：US17554456

申请日：2021-12-17

申请人： Sukru YEMENICIOGLU ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Seung-June CHOI

发明人： Sukru YEMENICIOGLU ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Seung-June CHOI

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L21/76816 ,  H01L21/76885

摘要： Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an interlayer dielectric layer. A plurality of parallel conductive lines is in the interlayer dielectric layer. The plurality of parallel conductive lines includes a first conductive line and a second conductive line. The first conductive line includes breaks therein with first and second dielectric plugs separating portions of the first conductive line, one of the portions between the first dielectric plug and the second dielectric plug and having a first dimension. The second conductive line includes first and second conductive line portions separated by an intervening conductive via structure, the conductive via structure separated from the first and second conductive line portions, and the conductive via structure having a second dimension parallel with the first dimension, the second dimension less than the first dimension.