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    Page buffer and multi-state nonvolatile memory device including the same
    1.
    发明授权
    Page buffer and multi-state nonvolatile memory device including the same 有权
    页面缓冲器和包括其的多状态非易失性存储器件

    公开(公告)号：US07480177B2

    公开(公告)日：2009-01-20

    申请号：US11870528

    申请日：2007-10-11

    申请人： Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

    发明人： Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

    摘要： According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

    摘要翻译： 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

    Multi-level nonvolatile semiconductor memory device and method for reading the same
    2.
    发明授权
    Multi-level nonvolatile semiconductor memory device and method for reading the same 有权
    多级非易失性半导体存储器件及其读取方法

    公开(公告)号：US07525850B2

    公开(公告)日：2009-04-28

    申请号：US11941101

    申请日：2007-11-16

    申请人： Dong Hyuk Chae ,  Young Ho Lim

    发明人： Dong Hyuk Chae ,  Young Ho Lim

    IPC分类号： G11C7/10

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

    摘要： A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

    摘要翻译： 提供一种包括存储器阵列，页缓冲器和行解码器的非易失性半导体存储器件。 存储器阵列包括多个非易失性存储器单元，位线和字线，并且行解码器被驱动以控制存储器阵列的字线。 页缓冲器电连接到位线，并包括主数据锁存器和子数据锁存器。 根据子数据锁存器的逻辑状态禁止主数据锁存器翻转的页缓冲器还包括主锁存块，子锁存块和锁存控制块。 主锁存块驱动主数据锁存器，并通过位线将主数据锁存器的逻辑状态映射到相应存储器单元的阈值电压。 子锁存块驱动子数据锁存器，其中子数据锁存器根据位线的电压电平翻转。 锁存控制块根据位线的电压电平有选择地翻转主数据锁存器，根据子数据锁存器的逻辑状态，锁存器控制块被禁用。

    Multi-level nonvolatile semiconductor memory device and method for reading the same
    3.
    发明申请
    Multi-level nonvolatile semiconductor memory device and method for reading the same 有权

    公开(公告)号：US20060268654A1

    公开(公告)日：2006-11-30

    申请号：US11416064

    申请日：2006-05-03

    申请人： Dong Hyuk Chae ,  Young Ho Lim

    发明人： Dong Hyuk Chae ,  Young Ho Lim

    IPC分类号： G11C8/00

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

    摘要： A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

    Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same
    4.
    发明授权
    Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same 有权
    半导体存储器件，用于改善冗余标志信号的响应余量和冗余驱动方法

    公开(公告)号：US07254076B2

    公开(公告)日：2007-08-07

    申请号：US11317303

    申请日：2005-12-27

    申请人： Dong Hyuk Chae ,  Young Ho Lim

    发明人： Dong Hyuk Chae ,  Young Ho Lim

    IPC分类号： G11C7/02

    CPC分类号： G11C7/1027 ,  G11C29/84

    摘要： A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresponding to an embedded address, and generating a redundancy flag signal, such that the embedded address is an address preceding the address of the memory cell of the normal cell array to be repaired by at least one clock.

    摘要翻译： 公开了具有适于修复正常存储器的冗余存储器的突发模式兼容半导体存储器件。 通过感测与嵌入地址相对应的内部地址的生成，并产生冗余标志信号来提高冗余标志信号和冗余驱动方法的响应余量，使得嵌入式地址是地址在存储器单元的地址之前的地址 正常的单元阵列将由至少一个时钟修复。

    Multi-level nonvolatile semiconductor memory device and method for reading the same
    5.
    发明授权
    Multi-level nonvolatile semiconductor memory device and method for reading the same 有权
    多级非易失性半导体存储器件及其读取方法

    公开(公告)号：US07313020B2

    公开(公告)日：2007-12-25

    申请号：US11416064

    申请日：2006-05-03

    申请人： Dong Hyuk Chae ,  Young Ho Lim

    发明人： Dong Hyuk Chae ,  Young Ho Lim

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

    摘要： A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

    摘要翻译： 提供一种包括存储器阵列，页缓冲器和行解码器的非易失性半导体存储器件。 存储器阵列包括多个非易失性存储器单元，位线和字线，并且行解码器被驱动以控制存储器阵列的字线。 页缓冲器电连接到位线，并包括主数据锁存器和子数据锁存器。 根据子数据锁存器的逻辑状态禁止主数据锁存器翻转的页缓冲器还包括主锁存块，子锁存块和锁存控制块。 主锁存块驱动主数据锁存器，并通过位线将主数据锁存器的逻辑状态映射到相应存储器单元的阈值电压。 子锁存块驱动子数据锁存器，其中子数据锁存器根据位线的电压电平翻转。 锁存控制块根据位线的电压电平有选择地翻转主数据锁存器，根据子数据锁存器的逻辑状态，锁存器控制块被禁用。

    Memory devices and methods for determining data of bit layers based on detected error bits
    8.
    发明授权
    Memory devices and methods for determining data of bit layers based on detected error bits 有权
    用于基于检测到的错误位来确定位层的数据的存储器件和方法

    公开(公告)号：US07903459B2

    公开(公告)日：2011-03-08

    申请号：US12232150

    申请日：2008-09-11

    申请人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    发明人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5621

    摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.

    摘要翻译： 公开了一种存储器件和存储器数据读取方法。 存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔， 单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。 在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压 检测到错误位。

    Memory programming method
    9.
    发明授权
    Memory programming method 有权
    内存编程方法

    公开(公告)号：US07885108B2

    公开(公告)日：2011-02-08

    申请号：US12382176

    申请日：2009-03-10

    申请人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

    发明人： Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong

    IPC分类号： G11C16/00

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3418

    摘要： A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage.

    摘要翻译： 存储器编程方法可以包括基于要在所述多个存储器单元中的至少一个存储器单元中编程的数据的模式来改变要改变的阈值电压的多个存储器单元中的至少一个，将程序条件电压施加到 所述至少一个所识别的存储器单元，直到所述至少一个所识别的存储单元的阈值电压被包括在第一阈值电压间隔内，从而调整所述至少一个识别的存储单元的阈值电压，并且对所述存储单元中的数据进行编程 具有调整的阈值电压的至少一个识别的存储器单元。