公开(公告)号：US10043583B2

公开(公告)日：2018-08-07

申请号：US15447357

申请日：2017-03-02

申请人： Sang-wan Nam ,  Dae-seok Byeon ,  Chi-weon Yoon

发明人： Sang-wan Nam ,  Dae-seok Byeon ,  Chi-weon Yoon

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/16

摘要： Provided are a nonvolatile memory device and a method of performing a sensing operation on the nonvolatile memory device. The nonvolatile memory device includes a control logic coupled to a memory cell array including strings. The control logic is configured to control a first weak-on voltage applied to an unselected string selection line and a second weak-on voltage applied to an unselected ground selection line during a setup interval of the sensing operation for sensing data from a selected string. The unselected string selection line and ground selection line are connected to a string selection transistor and a ground selection transistor, respectively, of a same unselected string. The selected string and the unselected string are connected to a same bit line. The first weak-on voltage and second weak-on voltage are respectively less than a threshold voltage of the string selection transistor and the ground selection transistor in the unselected string.

公开(公告)号：US09406359B2

公开(公告)日：2016-08-02

申请号：US14683186

申请日：2015-04-10

申请人： Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Chi-Weon Yoon

发明人： Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC分类号： G11C29/52 ,  G11C7/22 ,  G06F11/07 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C11/56 ,  G11C13/00 ,  G11C29/02 ,  G11C29/42 ,  G11C7/12

CPC分类号： G11C7/22 ,  G06F11/073 ,  G06F11/076 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/004 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2013/0054 ,  G11C2213/72

摘要： A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.

摘要翻译： 一种操作存储器系统的方法，包括：存储单元阵列中包含共同连接到第一信号线的存储单元; 根据单元区域划分存储单元，并且使用从多个读取参考中选择并且分别对应于每个单元区域的读取参考，独立地对设置在每个单元区域中的存储单元执行读取操作。

公开(公告)号：US08559235B2

公开(公告)日：2013-10-15

申请号：US13045661

申请日：2011-03-11

申请人： Chi Weon Yoon ,  Donghyuk Chae ,  Jae-Woo Park ,  Sang-Wan Nam

发明人： Chi Weon Yoon ,  Donghyuk Chae ,  Jae-Woo Park ,  Sang-Wan Nam

IPC分类号： G11C11/34

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

摘要： A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

公开(公告)号：US08189386B2

公开(公告)日：2012-05-29

申请号：US12458437

申请日：2009-07-13

申请人： June-hong Park ,  Chi-weon Yoon

发明人： June-hong Park ,  Chi-weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C2211/5621

摘要： A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation.

摘要翻译： 用于非易失性存储器件的编程方法包括执行编程操作以对存储器单元进行编程，当编程存储器单元被确定为包括不能被编程的存储器单元以及当前程序循环是最大程序循环时，确定是否 当编程失败的存储器单元的数量小于存储器的数量时，未编程的多个存储器单元对应于可以成功地进行ECC（错误校验和校正）的多个存储器单元 可以成功进行ECC的单元，读取数据，以确定是否能够编程的存储器单元的错误位的数量是否能够成功地进行ECC，并且当未编程的存储器单元可以成功地进行ECC时，结束 一个编程操作。

公开(公告)号：US07787305B2

公开(公告)日：2010-08-31

申请号：US12134648

申请日：2008-06-06

申请人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

摘要翻译： 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

公开(公告)号：US20100125699A1

公开(公告)日：2010-05-20

申请号：US12591198

申请日：2009-11-12

申请人： Jae-phil Kong ,  Chi-weon Yoon

发明人： Jae-phil Kong ,  Chi-weon Yoon

IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C2211/5641

摘要： Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data.

摘要翻译： 提供了闪速存储装置和闪存装置的读取方法。 多级单元闪存器件包括：存储单元阵列，包括存储主数据的主存储单元，存储指示单元的指示单元表示指示主存储单元的主数据的第一模式和第二模式之一的数据， 指示单元对应的; 以及输出单元，响应于与指示数据相对应的控制信号，从存储器单元阵列读取的主数据中的一个和强制数据将主数据的某些位值强制为模式特定数据的位值作为读取数据。

公开(公告)号：US20100027336A1

公开(公告)日：2010-02-04

申请号：US12458437

申请日：2009-07-13

申请人： June-hong Park ,  Chi-weon Yoon

发明人： June-hong Park ,  Chi-weon Yoon

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C2211/5621

摘要： A programming method for a non-volatile memory device includes performing a programming operation to program memory cells, when the programmed memory cells are determined to include memory cells that failed to be programmed and when a current program loop is a maximum program loop, determining whether a number of the memory cells that failed to be programmed corresponds to a number of memory cells that can successfully undergo ECC (error checking and correction), when the number of the memory cells that failed to be programmed is less than the number of the memory cells that can successfully undergo ECC, reading data so as to determine whether a number of error bits of the memory cells that failed to be programmed can successfully undergo ECC, and, when the memory cells that failed to be programmed can successfully undergo ECC, ending a programming operation.

摘要翻译： 用于非易失性存储器件的编程方法包括执行编程操作以对存储器单元进行编程，当编程存储器单元被确定为包括不能被编程的存储器单元以及当前程序循环是最大程序循环时，确定是否 当编程失败的存储器单元的数量小于存储器的数量时，未编程的多个存储器单元对应于可以成功地进行ECC（错误校验和校正）的多个存储器单元 可以成功进行ECC的单元，读取数据，以确定是否能够编程的存储器单元的错误位的数量是否能够成功地进行ECC，并且当未编程的存储器单元可以成功地进行ECC时，结束 一个编程操作。

公开(公告)号：US07474566B2

公开(公告)日：2009-01-06

申请号：US11763606

申请日：2007-06-15

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/06

CPC分类号： G11C16/3454

摘要： A method of driving a non-volatile memory device includes programming a plurality of memory cells based on a first data copied from a program data buffer to a verification data buffer, verifying the memory cells by overwriting a result of the verification of the programmed memory cells to a verification data buffer, and re-verifying the memory cells by repeating the programming and verifying operations at least once with respect to the memory cells that were successfully verified, based on the verification result written to the verification data buffer. A non-volatile memory device includes a program data buffer storing first data, a verification data buffer copying and storing the first data, a plurality of memory cells programmed based on the data stored in the verification data buffer, a comparator comparing data stored in the verification data buffer with data read out from the programmed memory cells and outputting comparison data generated based on a result of the comparison to the verification data buffer, and a control unit controlling the program data buffer, the verification data buffer, the memory cells, and the comparator to additionally program or verify the memory cells that were successfully verified, based on the first data.

摘要翻译： 驱动非易失性存储器件的方法包括：基于从程序数据缓冲器复制到验证数据缓冲器的第一数据来编程多个存储器单元，通过覆盖编程的存储器单元的验证结果来验证存储器单元 并且基于写入验证数据缓冲器的验证结果，通过重复对相对于成功验证的存储器单元的编程和验证操作至少一次来重新验证存储器单元。 非易失性存储装置包括存储第一数据的程序数据缓冲器，复制和存储第一数据的验证数据缓冲器，基于存储在验证数据缓冲器中的数据编程的多个存储器单元，比较存储在验证数据缓冲器中的数据的比较器 验证数据缓冲器，其具有从编程的存储器单元读出的数据，并输出基于与验证数据缓冲器的比较结果生成的比较数据;以及控制单元，控制程序数据缓冲器，验证数据缓冲器，存储器单元和 所述比较器基于所述第一数据额外编程或验证已成功验证的存储器单元。

公开(公告)号：US20080192540A1

公开(公告)日：2008-08-14

申请号：US12005366

申请日：2007-12-27

申请人： Jae-Phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： Jae-Phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G11C16/10

CPC分类号： G11C11/5628

摘要： In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

摘要翻译： 在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。 根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。 搜索到的数据位被编程为响应于同时编程的位的数量。 对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

公开(公告)号：US20070189105A1

公开(公告)日：2007-08-16

申请号：US11673996

申请日：2007-02-12

申请人： Chi-Weon YOON

发明人： Chi-Weon YOON

IPC分类号： G11C14/00 ,  G11C11/34 ,  G11C8/00

CPC分类号： G11C8/04 ,  G11C16/26

摘要： A flash memory device includes a memory cell array, an address buffer circuit including address buffers, each address buffer configured to store an address for a random read operation, a read circuit configured to sense data from the memory cell array in response to an address output from the address buffer circuit, an output data latch circuit configured to receive data sensed by the read circuit, and a control logic coupled to the address buffer circuit, the read circuit, and the output data latch circuit, and configured to control the output data latch circuit and the read circuit such that the output data latch circuit outputs first data read from the memory cell array substantially simultaneously as the read circuit senses second data from the memory cell array.

摘要翻译： 闪速存储器件包括存储单元阵列，包括地址缓冲器的地址缓冲器电路，每个地址缓冲器被配置为存储用于随机读取操作的地址;读取电路，被配置为响应于地址输出来检测来自存储器单元阵列的数据 从所述地址缓冲电路输出的数据锁存电路被配置为接收由所述读取电路感测的数据，以及控制逻辑，其耦合到所述地址缓冲器电路，所述读取电路和所述输出数据锁存电路，并且被配置为控制所述输出数据 锁存电路和读取电路，使得当读取电路从存储器单元阵列感测到第二数据时，输出数据锁存电路基本上同时输出从存储单元阵列读取的第一数据。