公开(公告)号：US20060124988A1

公开(公告)日：2006-06-15

申请号：US11291142

申请日：2005-11-30

申请人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

发明人： Sung-Hoi Hur ,  Jung-Dal Choi ,  Kyeong-Tae Kim ,  Jong-Ho Park ,  Jae-Duk Lee ,  Ki-Nam Kim

IPC分类号： H01L21/82 ,  H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor memory device is fabricated by forming an active region protruding from a semiconductor substrate, forming an isolation layer on the substrate adjacent opposing sidewalls of the active region, and forming a floating gate electrode on a surface of the active region between the opposing sidewalls thereof. The floating gate electrode is formed to extend beyond edges of the surface of the active region onto the isolation layer. A surface of the floating gate electrode adjacent the active region defines a plane, and the isolation layer is confined between the plane and the substrate. A control gate electrode is formed on a surface of the floating gate electrode opposite the active region. The control gate electrode may be formed to extend along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region. Related devices are also discussed.

摘要翻译： 半导体存储器件通过形成从半导体衬底突出的有源区域形成，在邻近有源区域的相对侧壁的衬底上形成隔离层，以及在其相对侧壁之间的有源区域的表面上形成浮栅电极 。 浮栅电极被形成为延伸超过有源区表面的边缘到隔离层上。 邻近有源区的浮栅电极的表面限定了一个平面，隔离层被限制在平面和衬底之间。 控制栅电极形成在浮动栅电极的与有源区相对的表面上。 控制栅电极可以被形成为沿着浮置栅电极的侧壁朝着衬底延伸超过由邻近有源区的浮栅的表面限定的平面。 还讨论了相关设备。

公开(公告)号：US20050023600A1

公开(公告)日：2005-02-03

申请号：US10921656

申请日：2004-08-19

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur ,  Sang-Bin Song ,  Jung-Dal Choi

IPC分类号： H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76802 ,  H01L27/115 ,  H01L27/11524

摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

公开(公告)号：US06677639B2

公开(公告)日：2004-01-13

申请号：US10188389

申请日：2002-07-01

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Byung-Kwan You ,  Sung-Hoi Hur

IPC分类号： H01L2976

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A non-volatile memory device and fabrication method thereof are provided. A floating region is formed on an active region on a substrate. Trenches define the active region. The floating region is made of an ONO layer. A gate electrode is formed on the floating region. A mask is formed on the gate electrode. A thermal oxidation is performed to make a sidewall oxide and a trench oxide on the sidewall of the gate electrode and the trench, respectively. As a result, the widths of the gate electrode and the active region become less than the width of the floating region, thereby forming protrusions at ends of the floating region. Isolation regions are formed in the trenches and include the sidewall oxide and the trench oxide. The isolation regions surround the protrusions. As a result, electric field induced on the sidewall of the floating region is decreased. Moreover, the thermal oxidation cures any damage to the sidewalls of the floating region. Accordingly, leakage current can be substantially suppressed at the boundary region between the isolation region and the floating region.

公开(公告)号：US06677200B2

公开(公告)日：2004-01-13

申请号：US10194182

申请日：2002-07-12

申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Sung-Hoi Hur

IPC分类号： H01L213366

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/66833 ,  Y10S438/954

摘要： A method of forming a non-volatile memory having a floating trap-type device is disclosed in the present invention. In the method, a relatively thick thermal oxide layer is formed at a semiconductor substrate and patterned to leave a thick thermal oxide pattern at a high-voltage region (a high-voltage region defining step). An oxide-nitride-oxide (ONO) layer is formed over substantially the entire surface (the substantial surface) of the semiconductor substrate and patterned to leave an ONO pattern at a cell memory region (a cell memory region defining step). After the high-voltage region defining step and the cell memory region defining step, a thermal oxidizing process is performed with respect to the semiconductor substrate where a low-voltage region is exposed, thereby forming a relatively thin gate insulation layer for a low-voltage type device (a low-voltage region defining region).

摘要翻译： 在本发明中公开了形成具有浮动陷阱型装置的非易失性存储器的方法。 在该方法中，在半导体衬底上形成相对较厚的热氧化物层，并将其图案化以在高电压区域（高电压区域限定步骤）处留下厚的热氧化物图案。 在半导体衬底的基本上整个表面（基本表面）上形成氧化物 - 氧化物（ONO）层，并将其图案化以在单元存储区（单元存储区定义步骤）处留下ONO图案。 在高电压区域定义步骤和电池存储区域限定步骤之后，对于暴露低电压区域的半导体衬底进行热氧化处理，从而形成用于低电压的较薄的栅极绝缘层 （低电压区域限定区域）。

公开(公告)号：US07391071B2

公开(公告)日：2008-06-24

申请号：US11233857

申请日：2005-09-23

申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

公开(公告)号：US07259421B2

公开(公告)日：2007-08-21

申请号：US11020920

申请日：2004-12-23

申请人： Sung-Hoi Hur ,  Jung-Dal Choi

发明人： Sung-Hoi Hur ,  Jung-Dal Choi

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

摘要翻译： 半导体存储器件包括其中具有沟槽的半导体衬底。 第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。 在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。 分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。 在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。 还讨论了相关方法。

公开(公告)号：US20060027855A1

公开(公告)日：2006-02-09

申请号：US11020920

申请日：2004-12-23

申请人： Sung-Hoi Hur ,  Jung-Dal Choi

发明人： Sung-Hoi Hur ,  Jung-Dal Choi

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

摘要翻译： 半导体存储器件包括其中具有沟槽的半导体衬底。 第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。 在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。 分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。 在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。 还讨论了相关方法。

公开(公告)号：US20070066003A1

公开(公告)日：2007-03-22

申请号：US11558634

申请日：2006-11-10

申请人： Sung-Hoi Hur ,  Jung-Dal Choi

发明人： Sung-Hoi Hur ,  Jung-Dal Choi

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

摘要翻译： 半导体存储器件包括其中具有沟槽的半导体衬底。 第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。 在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。 分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。 在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。 还讨论了相关方法。

公开(公告)号：US07501322B2

公开(公告)日：2009-03-10

申请号：US11558634

申请日：2006-11-10

申请人： Sung-Hoi Hur ,  Jung-Dal Choi

发明人： Sung-Hoi Hur ,  Jung-Dal Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.

摘要翻译： 半导体存储器件包括其中具有沟槽的半导体衬底。 第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。 在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。 分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。 在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。 还讨论了相关方法。

公开(公告)号：US20060063331A1

公开(公告)日：2006-03-23

申请号：US11233857

申请日：2005-09-23

申请人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

发明人： Min-Cheol Park ,  Sung-Hoi Hur ,  Jung-Dal Choi ,  Ji-Hwon Lee

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。 衬底中的沟槽限定邻近沟槽的衬底的有源区。 器件隔离层沿着沟槽在衬底上。 隧道绝缘层位于衬底的有源区上。 浮动栅极位于与衬底的有源区相对的隧道绝缘层上。 埋置的浮动栅极位于沟槽中的器件隔离层上。 隔间电介质层在浮栅和埋入浮栅之间并且延伸。 控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。