公开(公告)号：US09012977B2

公开(公告)日：2015-04-21

申请号：US14154834

申请日：2014-01-14

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US20130075807A1

公开(公告)日：2013-03-28

申请号：US13684857

申请日：2012-11-26

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

IPC分类号： H01L29/792

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US20140124846A1

公开(公告)日：2014-05-08

申请号：US14154834

申请日：2014-01-14

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

IPC分类号： H01L27/02

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US08319275B2

公开(公告)日：2012-11-27

申请号：US12698542

申请日：2010-02-02

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

IPC分类号： H01L29/792 ,  H01L29/66 ,  H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US20100213527A1

公开(公告)日：2010-08-26

申请号：US12698542

申请日：2010-02-02

申请人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

发明人： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Sunghoi Hur ,  Jaehoon Jang ,  Su-Youn Yi

IPC分类号： H01L27/11 ,  H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

摘要翻译： 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US20100133606A1

公开(公告)日：2010-06-03

申请号：US12592404

申请日：2009-11-24

申请人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.

摘要翻译： 一种三维半导体存储器件包括字形线和栅极层间绝缘层，其交替地层叠在半导体衬底上，同时在水平方向上延伸，垂直沟道层面向字线并从半导体衬底向上延伸，并且沟道 衬垫，其从垂直沟道层延伸并且设置在栅极层间绝缘层的最上层的栅极层间绝缘层上。

公开(公告)号：US20100097859A1

公开(公告)日：2010-04-22

申请号：US12584674

申请日：2009-09-10

申请人： Sunil Shim ,  Sunghoi Hur ,  Younggoan Jang ,  Jinho Kim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Sunil Shim ,  Sunghoi Hur ,  Younggoan Jang ,  Jinho Kim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： G11C16/04 ,  G11C5/02

CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578

摘要： A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.

摘要翻译： 具有三维结构的非易失性存储器件包括第一字线堆叠，其中第一字线被堆叠; 第二字线堆叠，其中平行于第一字线的第二字线被堆叠; 连接第一字线的第一连接线; 以及连接第二字线的第二连接线。 每个第一连接线连接位于公共层的第一字线，每个第二连接线连接位于公共层的第二字线，并且至少一个第二字线堆叠设置在一对第一字之间 线堆叠

公开(公告)号：US08107289B2

公开(公告)日：2012-01-31

申请号：US13217627

申请日：2011-08-25

申请人： Sunil Shim ,  Sunghoi Hur ,  Younggoan Jang ,  Jinho Kim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Sunil Shim ,  Sunghoi Hur ,  Younggoan Jang ,  Jinho Kim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： G11C11/34

CPC分类号： G11C5/02 ,  G11C5/063 ,  G11C8/14 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578

摘要： A nonvolatile memory device having a three-dimensional structure includes first word line stacks in which first word lines are stacked; second word line stacks in which second word lines parallel to the first word lines are stacked; first connection lines connecting the first word lines; and second connection lines connecting the second word lines. Each of the first connection lines connects the first word lines located at a common layer, each of the second connection lines connects the second word lines located at a common layer and at least one second word line stack is disposed between a pair of the first word line stacks.

摘要翻译： 具有三维结构的非易失性存储器件包括第一字线堆叠，其中第一字线被堆叠; 第二字线堆叠，其中平行于第一字线的第二字线被堆叠; 连接第一字线的第一连接线; 以及连接第二字线的第二连接线。 每个第一连接线连接位于公共层的第一字线，每个第二连接线连接位于公共层的第二字线，并且至少一个第二字线堆叠设置在一对第一字之间 线堆叠

公开(公告)号：US20130248983A1

公开(公告)日：2013-09-26

申请号：US13898032

申请日：2013-05-20

申请人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.

摘要翻译： 一种三维半导体存储器件包括字形线和栅极层间绝缘层，其交替地层叠在半导体衬底上，同时在水平方向上延伸，垂直沟道层面向字线并从半导体衬底向上延伸，并且沟道 衬垫，其从垂直沟道层延伸并且设置在栅极层间绝缘层的最上层的栅极层间绝缘层上。

公开(公告)号：US08445954B2

公开(公告)日：2013-05-21

申请号：US12592404

申请日：2009-11-24

申请人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

发明人： Younggoan Jang ,  Sunghoi Hur ,  Jinho Kim ,  Sunil Shim ,  Su-Youn Yi ,  HuiChang Moon

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.