公开(公告)号：US09917094B2

公开(公告)日：2018-03-13

申请号：US14920223

申请日：2015-10-22

Applicant: Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

Inventor： Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

IPC: G11C5/06 ,  H01L27/11565 ,  G11C7/00 ,  H01L23/48 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/02

CPC classification number: H01L27/11565 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C7/18 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

公开(公告)号：US20160284419A1

公开(公告)日：2016-09-29

申请号：US15176269

申请日：2016-06-08

Applicant: Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

Inventor： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract translation: 非易失性存储器件，其操作方法和包括其的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。

公开(公告)号：US09329625B2

公开(公告)日：2016-05-03

申请号：US13825496

申请日：2011-07-16

Applicant: Hongchun Park ,  Hansoo Kim

Inventor： Hongchun Park ,  Hansoo Kim

IPC: G06F3/044 ,  G06F1/16 ,  G06F3/045 ,  H05K1/09 ,  G06F3/041

CPC classification number: G06F3/0416 ,  G06F1/16 ,  G06F3/041 ,  G06F3/0412 ,  G06F3/044 ,  G06F3/045 ,  G06F2203/04103 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K1/092 ,  H05K1/111 ,  H05K2201/0145 ,  H05K2201/0154 ,  H01L2924/00

Abstract: The present invention relates to a touch screen panel and a touch screen assembly including the touch screen panel, the touch screen panel including a substrate; a transparent electrode layer formed on the substrate; a plurality of conductive wires electrically connected to the transparent electrode layer; an insulation film formed on the transparent electrode layer; and a plurality of conductive line, each of which is electrically connected to each of the plurality of conductive wires inside the insulation film, extended to an outside of the insulation film and exposed therefrom, whereby a PCB and conductive wires can be improved in electrical reliability.

Abstract translation: 本发明涉及触摸屏面板和包括触摸屏面板的触摸屏组件，触摸屏面板包括基板; 形成在所述基板上的透明电极层; 电连接到透明电极层的多个导线; 形成在所述透明电极层上的绝缘膜; 以及多个导电线，每个导电线电连接到绝缘膜内部的多个导线中的每一个，延伸到绝缘膜的外部并暴露于绝缘膜的外部，从而可以提高PCB和导线的电可靠性 。

公开(公告)号：US20150380093A1

公开(公告)日：2015-12-31

申请号：US14849029

申请日：2015-09-09

Applicant: Sun-il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

Inventor： Sun-il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/12 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract translation: 非易失性存储器件，其操作方法和包括其的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。

公开(公告)号：US09177613B2

公开(公告)日：2015-11-03

申请号：US14018885

申请日：2013-09-05

Applicant: Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

Inventor： Wookhyoung Lee ,  Jongsik Chun ,  Sunil Shim ,  Jaeyoung Ahn ,  Juyul Lee ,  Kihyun Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Jaehoon Jang ,  Wonseok Cho

IPC: G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  G11C7/18 ,  H01L27/115 ,  H01L27/02

CPC classification number: H01L27/11565 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C7/18 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

Abstract translation: 提供了一种半导体器件，其包括设置在基板上的栅极结构，插入在栅极结构之间的分离绝缘层以及通过每个栅极结构连接到基板的多个单元柱。 每个栅极结构可以包括垂直堆叠在基板上的水平电极，并且相邻的单元柱之间的间隔是不均匀的。

公开(公告)号：US08913433B2

公开(公告)日：2014-12-16

申请号：US13093320

申请日：2011-04-25

Applicant: Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

Inventor： Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/115 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11582

Abstract: Reading methods of nonvolatile memory devices including a substrate and a plurality of memory cells which are stacked in a direction intersecting the substrate. The reading methods apply a bit line voltage to a plurality of bit lines and apply a first string selection line voltage to at least one selected string selection line. The reading methods apply a second string selection line voltage to at least one unselected string selection line and apply a read voltage to a plurality of word lines. The reading methods apply a first ground selection line voltage to at least one selected ground selection line and apply a second ground selection line voltage to at least one unselected ground selection line.

Abstract translation: 非易失性存储器件的读取方法包括在与衬底交叉的方向上堆叠的衬底和多个存储单元。 读取方法将位线电压施加到多个位线，并将第一串选择线电压施加到至少一个所选择的串选择线。 读取方法将第二串选择线电压施加到至少一个未选择的串选择线，并将读电压施加到多个字线。 读取方法将第一接地选择线电压施加到至少一个所选择的接地选择线，并将第二接地选择线电压施加到至少一个未选择的接地选择线。

公开(公告)号：US20140183756A1

公开(公告)日：2014-07-03

申请号：US14142158

申请日：2013-12-27

Applicant: Sung-Min HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Wonseok CHO

Inventor： Sung-Min HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Wonseok CHO

IPC: H01L23/498

CPC classification number: G11C16/0483 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

Abstract translation: 三维半导体器件包括在第一和第二接触区域之间具有单元阵列区域的衬底。 第一堆叠包括垂直设置在基板上的多个第一电极，第二堆叠包括垂直设置在第一堆叠上的多个第二电极。 第二堆叠被布置成暴露第一接触区域上的第一电极的端部并且在第二接触区域上重叠第一电极的端部。

公开(公告)号：US20140124846A1

公开(公告)日：2014-05-08

申请号：US14154834

申请日：2014-01-14

Applicant: Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

Inventor： Sunil Shim ,  Jaehun Jeong ,  Hansoo Kim ,  Su-Youn Yi ,  Jaehoon Jang ,  Sunghoi Hur

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract translation: 提供了一种半导体存储器件。 在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。 第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

公开(公告)号：US08603906B2

公开(公告)日：2013-12-10

申请号：US13779334

申请日：2013-02-27

Applicant: Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

Inventor： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

Abstract translation: 提供一种三维半导体存储器件。 三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。 多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。 每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

公开(公告)号：US08592912B2

公开(公告)日：2013-11-26

申请号：US13106481

申请日：2011-05-12

Applicant: Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jae-Joo Shim

IPC: H01L29/78

CPC classification number: H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：多个导电图案，其堆叠在基板上并彼此间隔开;以及焊盘图案，其包括从多个导电图案中的任一个的一端平行于基板延伸的平坦部分， 以及从所述平坦部分的顶表面向上延伸的着陆侧壁部分，其中所述着陆侧壁部分在平行于所述基板并且垂直于所述第一方向的第二方向上的一部分的宽度小于所述平坦部分的宽度 。