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    Low jitter clock for a physical media access sublayer on a field programmable gate array
    2.
    发明授权
    Low jitter clock for a physical media access sublayer on a field programmable gate array 有权
    用于现场可编程门阵列上的物理介质访问子层的低抖动时钟

    公开(公告)号：US06911842B1

    公开(公告)日：2005-06-28

    申请号：US10090239

    申请日：2002-03-01

    申请人： Atul V. Ghia ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Philip D. Costello ,  Hare K. Verma

    发明人： Atul V. Ghia ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Philip D. Costello ,  Hare K. Verma

    IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K17/693 ,  H03K19/173 ,  H03K19/77

    CPC分类号： G06F1/10

    摘要： A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.

    摘要翻译： 提供了支持多千兆位收发器（MGT）的可编程逻辑器件（PLD）。 PLD包括用于接收一个或多个高质量差分时钟信号的一对或多对共享时钟焊盘。 专用时钟跟踪将每对共享时钟接口耦合到PLD上的一个或多个MGT。 每个MGT包括时钟多路复用器电路，其允许将高质量差分时钟信号中的一个作为MGT的参考时钟信号进行路由。 时钟多路复用器电路被设计成使得高质量时钟信号不会增加显着的抖动。 时钟多路复用器电路还可以将由PLD接收的通用时钟信号作为MGT的较低质量参考时钟信号。 可以降低由时钟多路复用器电路路由的参考时钟信号，为MGT的物理编码子层提供参考时钟。

    Data monitoring for single event upset in a programmable logic device
    3.
    发明授权
    Data monitoring for single event upset in a programmable logic device 有权
    可编程逻辑器件中单事件不正常的数据监控

    公开(公告)号：US07109746B1

    公开(公告)日：2006-09-19

    申请号：US10806697

    申请日：2004-03-22

    申请人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

    发明人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/1776

    摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

    摘要翻译： 描述用于错误检测的数据监视的方法和装置。 可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。 功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。 主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。 辅助地址线耦合到与功能发生器相关联的存储器单元组。 掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

    Data monitoring for single event upset in a programmable logic device
    4.
    发明授权
    Data monitoring for single event upset in a programmable logic device 有权
    可编程逻辑器件中单事件不正常的数据监控

    公开(公告)号：US07283409B1

    公开(公告)日：2007-10-16

    申请号：US11503824

    申请日：2006-08-14

    申请人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

    发明人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

    IPC分类号： G11C29/00 ,  G01R31/28

    CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/1776

    摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

    摘要翻译： 描述用于错误检测的数据监视的方法和装置。 可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。 功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。 主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。 辅助地址线耦合到与功能发生器相关联的存储器单元组。 掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

    Determining timing paths within a circuit block of a programmable integrated circuit
    5.
    发明授权
    Determining timing paths within a circuit block of a programmable integrated circuit 有权
    确定可编程集成电路的电路块内的定时路径

    公开(公告)号：US08117577B1

    公开(公告)日：2012-02-14

    申请号：US12361516

    申请日：2009-01-28

    申请人： Vasisht M. Vadi ,  Alvin Y. Ching ,  Subodh Kumar ,  Richard D. Freeman ,  Ian L. McEwen ,  Philip R. Haratsaris ,  Jaime D. Lujan ,  Eric M. Schwarz

    发明人： Vasisht M. Vadi ,  Alvin Y. Ching ,  Subodh Kumar ,  Richard D. Freeman ,  Ian L. McEwen ,  Philip R. Haratsaris ,  Jaime D. Lujan ,  Eric M. Schwarz

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5054 ,  G06F17/5031 ,  G06F2217/84

    摘要： A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.

    摘要翻译： 识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。 该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。 该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径 多个子路径，并输出定时路径。

    Digital signal processing block with preadder stage
    7.
    发明授权
    Digital signal processing block with preadder stage 有权
    数字信号处理块，带舞台

    公开(公告)号：US08543635B2

    公开(公告)日：2013-09-24

    申请号：US12360836

    申请日：2009-01-27

    申请人： James M. Simkins ,  Alvin Y. Ching ,  John M. Thendean ,  Vasisht M. Vadi ,  Chi Fung Poon ,  Muhammad Asim Rab

    发明人： James M. Simkins ,  Alvin Y. Ching ,  John M. Thendean ,  Vasisht M. Vadi ,  Chi Fung Poon ,  Muhammad Asim Rab

    IPC分类号： G06F7/50 ,  H01L25/00

    CPC分类号： G06F7/5443 ,  H03H17/06 ,  H03H2220/04 ,  H03H2220/06 ,  H03K19/17732

    摘要： A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.

    摘要翻译： 描述了具有用于集成电路的前级的数字信号处理块。 数字信号处理块包括一个前级和一个控制总线。 控制总线耦合到前级，用于动态地控制前级的操作。 前级级包括：耦合到控制总线的第一多路复用器的第一输入端口; 耦合到控制总线的第一逻辑门的第二输入端口; 耦合到控制总线的第二逻辑门的​​第三输入端口; 以及耦合到控制总线的加法器/减法器的第四输入端口。

    Glitchless dynamic multiplexer with synchronous and asynchronous controls
    8.
    发明授权
    Glitchless dynamic multiplexer with synchronous and asynchronous controls 有权
    无差错动态多路复用器，具有同步和异步控制

    公开(公告)号：US06975145B1

    公开(公告)日：2005-12-13

    申请号：US10453235

    申请日：2003-06-02

    申请人： Vasisht M. Vadi ,  Steven P. Young

    发明人： Vasisht M. Vadi ,  Steven P. Young

    IPC分类号： G06F1/04 ,  H03K3/00 ,  H03K17/00 ,  H03K17/693

    CPC分类号： G06F1/04 ,  H03K17/005 ,  H03K17/693

    摘要： Described are glitchless clock control circuits capable of switching away from a failed clock. One embodiment supports three basic functions: clock select, clock enable, and clock ignore. The clock-select function provides a selected one of a plurality of clock signals on a clock-distribution node. The select signals used to switch between clock signals need to be synchronous with any of the clock signals. The clock-enable function allows the clock control circuit to synchronously block or pass a selected clock signal. Finally, the clock-ignore function allows the clock control circuit to ignore a selected clock if necessary, for example, to switch away from a failed clock.

    摘要翻译： 描述了能够切换故障时钟的无故障时钟控制电路。 一个实施例支持三个基本功能：时钟选择，时钟使能和时钟忽略。 时钟选择功能在时钟分配节点上提供多个时钟信号中选择的一个。 用于在时钟信号之间切换的选择信号需要与任何时钟信号同步。 时钟使能功能允许时钟控制电路同步阻塞或传递选定的时钟信号。 最后，如果需要，时钟忽略功能允许时钟控制电路忽略所选择的时钟，例如，从故障时钟切换。