公开(公告)号：US07187709B1

公开(公告)日：2007-03-06

申请号：US10090250

申请日：2002-03-01

申请人： Suresh M. Menon ,  Atul V. Ghia ,  Warren E. Cory ,  Paul T. Sasaki ,  Philip M. Freidin ,  Santiago G. Asuncion ,  Philip D. Costello ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Hare K. Verma

发明人： Suresh M. Menon ,  Atul V. Ghia ,  Warren E. Cory ,  Paul T. Sasaki ,  Philip M. Freidin ,  Santiago G. Asuncion ,  Philip D. Costello ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Hare K. Verma

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： G06F15/7867

摘要： One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.

摘要翻译： 一个或多个可配置的收发器可以在集成电路上制造。 收发器包含各种组件，具有可通过打开或关闭配置存储单元来配置的选项。 该集成电路还可以包含可编程织物。 收发器中的其他组件可以具有由可编程结构控制的选项。 集成电路还可以包含一个或多个处理器核。 处理器核心和收发器可以通过通过可编程结构的多个信号路径连接。

公开(公告)号：US06911842B1

公开(公告)日：2005-06-28

申请号：US10090239

申请日：2002-03-01

申请人： Atul V. Ghia ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Philip D. Costello ,  Hare K. Verma

发明人： Atul V. Ghia ,  Vasisht M. Vadi ,  Adebabay M. Bekele ,  Philip D. Costello ,  Hare K. Verma

IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K17/693 ,  H03K19/173 ,  H03K19/77

CPC分类号： G06F1/10

摘要： A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.

摘要翻译： 提供了支持多千兆位收发器（MGT）的可编程逻辑器件（PLD）。 PLD包括用于接收一个或多个高质量差分时钟信号的一对或多对共享时钟焊盘。 专用时钟跟踪将每对共享时钟接口耦合到PLD上的一个或多个MGT。 每个MGT包括时钟多路复用器电路，其允许将高质量差分时钟信号中的一个作为MGT的参考时钟信号进行路由。 时钟多路复用器电路被设计成使得高质量时钟信号不会增加显着的抖动。 时钟多路复用器电路还可以将由PLD接收的通用时钟信号作为MGT的较低质量参考时钟信号。 可以降低由时钟多路复用器电路路由的参考时钟信号，为MGT的物理编码子层提供参考时钟。

公开(公告)号：US07109746B1

公开(公告)日：2006-09-19

申请号：US10806697

申请日：2004-03-22

申请人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

发明人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/1776

摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

摘要翻译： 描述用于错误检测的数据监视的方法和装置。 可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。 功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。 主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。 辅助地址线耦合到与功能发生器相关联的存储器单元组。 掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

公开(公告)号：US07283409B1

公开(公告)日：2007-10-16

申请号：US11503824

申请日：2006-08-14

申请人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

发明人： Martin L. Voogel ,  David P. Schultz ,  Vasisht M. Vadi ,  Philip D. Costello ,  Venu M. Kondapalli

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： H03K19/17748 ,  H03K19/17732 ,  H03K19/1776

摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

摘要翻译： 描述用于错误检测的数据监视的方法和装置。 可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。 功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。 主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。 辅助地址线耦合到与功能发生器相关联的存储器单元组。 掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

公开(公告)号：US07265576B1

公开(公告)日：2007-09-04

申请号：US11152736

申请日：2005-06-14

申请人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

发明人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)×1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N−1))×2 RAM) having fewer than N (e.g., N−1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N−1)-bit shift register or two 2**(N−2)-bit shift registers.

摘要翻译： 当编程为用作随机存取存储器（RAM）时，可编程查找表可选地向可编程集成电路的互连结构提供两个输入信号和两个输出信号。 集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT）。 LUT可以被配置为用作具有耦合到互连结构的N个输入地址信号和耦合到互连结构的一个输出信号的单位宽RAM（例如，（2 ** N）x1 RAM），或者作为 具有小于N（例如，N-1）个输入地址信号的耦合到互连结构的多位宽RAM（例如，（2 **（N-1））×2 RAM）以及耦合到互连结构的至少两个输出信号 互连结构。 可选地，LUT也可以被配置为移位寄存器逻辑，例如2 **（N-1）位移位寄存器或两个2 **（N-2）位移位寄存器。

公开(公告)号：US07256612B1

公开(公告)日：2007-08-14

申请号：US11151796

申请日：2005-06-14

申请人： Steven P. Young ,  Tien Pham ,  Philip D. Costello

发明人： Steven P. Young ,  Tien Pham ,  Philip D. Costello

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： H03K19/17772 ,  G06F7/505 ,  G06F7/53 ,  H03K19/17728 ,  H03K19/17736

摘要： A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry chain for the programmable logic block. A carry initialization circuit has an output terminal coupled to a data input terminal of a first carry multiplexer in the carry chain. The carry initialization circuit is controlled by configuration memory cells of the programmable logic block to select one of a carry in signal, a power high signal, a ground signal, and (optionally) a signal from an interconnect structure of the logic block. Thus, an initialization value (e.g., power high or ground) can be provided to the carry chain without consuming other programmable resources within the logic block.

摘要翻译： 一个可编程逻辑块为进位逻辑块提供可编程的初始化值，而不需要消耗用户的逻辑资源。 示例性可编程逻辑块包括耦合在一起以形成可编程逻辑块的进位链的两个或多个进位多路复用器。 进位初始化电路具有耦合到进位链中的第一进位多路复用器的数据输入端的输出端。 携带初始化电路由可编程逻辑块的配置存储器单元控制，以选择进位信号，功率高信号，接地信号和（可选地）来自逻辑块的互连结构的信号之一。 因此，可以向进位链提供初始化值（例如，功率高或接地），而不消耗逻辑块内的其他可编程资源。

公开(公告)号：US07518394B1

公开(公告)日：2009-04-14

申请号：US11703862

申请日：2007-02-07

申请人： Manoj Chirania ,  Philip D. Costello

发明人： Manoj Chirania ,  Philip D. Costello

IPC分类号： H03K19/00

CPC分类号： H03K19/1776 ,  H03K19/17764

摘要： A method and apparatus is provided for the implementation of a process monitor vehicle (PMV) for memory cells. The memory cell PMV is useful in characterizing drive strength of the N-type and P-type field effect transistors (FETs) that are used to implement the memory cell. The memory cell PMV may be used, for example, to measure the amount of margin available for memory cell flips and how process variation affects the memory cell write margin. The memory cell PMV is implemented as a plurality of shift register bits interconnected as a ring oscillator, where each shift register bit is comprised of a memory cell. By adjusting the drive current for each memory cell and measuring the resultant change in oscillation frequency of the ring oscillator, information may be obtained concerning process variation and its effect on memory cell performance.

摘要翻译： 提供了一种用于实现用于存储器单元的过程监视器车辆（PMV）的方法和装置。 存储单元PMV可用于表征用于实现存储单元的N型和P型场效应晶体管（FET）的驱动强度。 存储单元PMV可以用于例如测量可用于存储器单元翻转的余量以及处理变化如何影响存储器单元写入余量。 存储单元PMV被实现为作为环形振荡器互连的多个移位寄存器位，其中每个移位寄存器位由存储单元组成。 通过调整每个存储单元的驱动电流并测量环形振荡器的振荡频率的变化，可以获得关于过程变化及其对存储单元性能的影响的信息。

公开(公告)号：US07075333B1

公开(公告)日：2006-07-11

申请号：US10925259

申请日：2004-08-24

申请人： Kamal Chaudhary ,  Philip D. Costello ,  Venu M. Kondapalli

发明人： Kamal Chaudhary ,  Philip D. Costello ,  Venu M. Kondapalli

IPC分类号： H03K19/173 ,  H03K19/177 ,  H01L25/00 ,  G06F7/38

CPC分类号： H03K19/1737 ,  H03K19/17728

摘要： Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is included between each memory cell and the corresponding data input terminal of a first multiplexer. Each function select multiplexer has a first data input terminal coupled to the corresponding memory cell, a second data input terminal coupled to an external input terminal, and a select terminal controlled by a value stored in a function select memory cell. When a first value is stored in the function select memory cell, the programmable circuit functions in the same fashion as a known LUT. When a second value is stored in the function select memory cell, the programmable circuit functions as a wide multiplexer, with the data input values being provided by the external input terminals.

摘要翻译： 可选地编程为用作查找表（LUT）或多路复用器的电路，以及包括这些可编程电路的集成电路。 每个存储单元和第一多路复用器的对应的数据输入端之间包括功能选择多路复用器。 每个功能选择多路复用器具有耦合到对应的存储器单元的第一数据输入端子，耦合到外部输入端子的第二数据输入端子和由存储在功能选择存储器单元中的值控制的选择端子。 当第一值存储在功能选择存储单元中时，可编程电路以与已知LUT相同的方式起作用。 当第二个值存储在功能选择存储单元中时，可编程电路用作宽多路复用器，数据输入值由外部输入端提供。

公开(公告)号：US07215138B1

公开(公告)日：2007-05-08

申请号：US11152590

申请日：2005-06-14

申请人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

发明人： Venu M. Kondapalli ,  Trevor J. Bauer ,  Manoj Chirania ,  Philip D. Costello ,  Steven P. Young

IPC分类号： H03K19/173

CPC分类号： H03K19/1736 ,  H03K19/17728 ,  H03K19/1776

摘要： A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N−1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N−2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.

摘要翻译： 用于集成电路（IC）的可编程查找表可选地在编程为用作移位寄存器逻辑时提供两个输入信号和两个输出信号到可编程IC的互连结构。 根据一个实施例，集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT），其中N是整数。 LUT可以被配置为用作具有输入信号移位和耦合到互连结构的一个输出信号的（2 **（N-1））位移位寄存器，或者作为二（2 **（N- 2）） - 具有耦合到互连结构的输入信号中的两个移位和两个输出信号的位移位寄存器。 在一些实施例中，移位寄存器的每个位包括LUT的两个存储单元，用作主锁存器的第一存储器单元和用作从锁存器的第二存储器单元。

公开(公告)号：US07109783B1

公开(公告)日：2006-09-19

申请号：US10847966

申请日：2004-05-18

申请人： Venu M. Kondapalli ,  Martin L. Voogel ,  Philip D. Costello

发明人： Venu M. Kondapalli ,  Martin L. Voogel ,  Philip D. Costello

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.

摘要翻译： 描述了用于调整集成电路内的电压的方法和装置。 例如，电压调节器接收第一参考电压并产生调节电压。 比较器包括用于接收第二参考电压的第一输入端和用于接收调节电压的第二输入端。 比较器包括偏移电压。 比较器产生指示第二参考电压和调节电压之间的差是否大于预定偏移电压的控制信号。 钳位电路响应于控制信号将调节电压钳位到第二参考电压。 在另一示例中，钳位电路被去除，并且多路复用器选择要耦合到电压调节器的第一参考电压或第二参考电压。 通过比较第一参考电压和第二参考电压的比较器的输出来控制多路复用器。