公开(公告)号：US20110073954A1

公开(公告)日：2011-03-31

申请号：US12961168

申请日：2010-12-06

申请人： Susumu AKAMATSU ,  Masafumi Tsutsui ,  Yoshinori Takami

发明人： Susumu AKAMATSU ,  Masafumi Tsutsui ,  Yoshinori Takami

IPC分类号： H01L27/092

CPC分类号： H01L21/823462 ,  H01L21/823493 ,  H01L27/11

摘要： In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

摘要翻译： 在第一部分的半导体衬底中，形成在半导体衬底的内部具有杂质浓度峰值的沟道区，在第二部分和第三部分的半导体衬底中，在 形成靠近基板表面的位置。 然后，在第一部分，第二部分和第三部分中形成延伸区域。 之后，对基板进行热处理以消除延伸区域中产生的缺陷。 然后，使用栅电极和侧壁间隔物作为掩模，在第一部分，第二部分和第三部分中形成源极/漏极区域。

公开(公告)号：US20100248438A1

公开(公告)日：2010-09-30

申请号：US12796412

申请日：2010-06-08

申请人： Susumu AKAMATSU ,  Masafumi Tsutsui ,  Yoshinori Takami

发明人： Susumu AKAMATSU ,  Masafumi Tsutsui ,  Yoshinori Takami

IPC分类号： H01L21/8236

CPC分类号： H01L21/823462 ,  H01L21/823493 ,  H01L27/11

摘要： In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

摘要翻译： 在第一部分的半导体衬底中，形成在半导体衬底的内部具有杂质浓度峰值的沟道区，在第二部分和第三部分的半导体衬底中，在 形成靠近基板表面的位置。 然后，在第一部分，第二部分和第三部分中形成延伸区域。 之后，对基板进行热处理以消除延伸区域中产生的缺陷。 然后，使用栅电极和侧壁间隔物作为掩模，在第一部分，第二部分和第三部分中形成源极/漏极区域。

公开(公告)号：US20120056271A1

公开(公告)日：2012-03-08

申请号：US13293579

申请日：2011-11-10

申请人： Susumu AKAMATSU

发明人： Susumu AKAMATSU

IPC分类号： H01L27/092

CPC分类号： H01L21/823462 ,  H01L21/76224 ,  H01L21/823456 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device includes a first, second, and third MIS transistors of a first conductivity type respectively including a first, second, and third gate electrodes on a first, second, and third active regions of a semiconductor substrate with a first, second, and third gate insulating films interposed therebetween. The first gate insulating film is formed of a first silicon oxide film and a first high-k insulating film on the first silicon oxide film. The second gate insulating film is formed of a second silicon oxide film and a second high-k insulating film on the second silicon oxide film. The third gate insulating film is formed of a third silicon oxide film and a third high-k insulating film on the third silicon oxide film. The second silicon oxide film has a same thickness as the first silicon oxide film, and a greater thickness than the third silicon oxide film.

摘要翻译： 半导体器件包括第一导电类型的第一，第二和第三MIS晶体管，其分别包括半导体衬底的第一，第二和第三有源区上的第一，第二和第三栅电极，第一，第二和第三栅电极具有第一，第二和第三栅电极， 第三栅绝缘膜插入其间。 第一栅极绝缘膜由第一氧化硅膜和第一高k绝缘膜形成在第一氧化硅膜上。 第二栅极绝缘膜由第二氧化硅膜和第二高k绝缘膜形成在第二氧化硅膜上。 第三栅极绝缘膜由第三氧化硅膜和第三高k绝缘膜形成在第三氧化硅膜上。 第二氧化硅膜具有与第一氧化硅膜相同的厚度，并且具有比第三氧化硅膜更大的厚度。

公开(公告)号：US20120280328A1

公开(公告)日：2012-11-08

申请号：US13554386

申请日：2012-07-20

申请人： Yoshiya MORIYAMA ,  Hiromasa FUJIMOTO ,  Satoru ITOU ,  Susumu AKAMATSU ,  Hiroshi OHKAWA

发明人： Yoshiya MORIYAMA ,  Hiromasa FUJIMOTO ,  Satoru ITOU ,  Susumu AKAMATSU ,  Hiroshi OHKAWA

IPC分类号： H01L27/092

CPC分类号： H01L29/7843 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L23/485 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1

摘要翻译： 半导体器件包括第一导电型第一MIS晶体管和第二导电型第二MIS晶体管。 第一和第二MIS晶体管包括形成在由半导体衬底的分离区围绕的第一和第二有源区上的第一和第二栅极绝缘膜，以及形成在第一和第二栅极绝缘上的第一和第二栅电极 电影。 第一和第二栅极绝缘膜在分离区域的第一分离区域上彼此分离。 在第一和第二有源区域的第一端之间的距离为第一和第二有源区域之间的距离，第一分隔区域彼此相对，并且从第一有源区域的第一端到第一栅极绝缘膜的第一端的突出量d1 在第一分离区域建立关系d1 <0.5s。