公开(公告)号：US07474548B2

公开(公告)日：2009-01-06

申请号：US11637939

申请日：2006-12-13

申请人： Yoshiya Moriyama ,  Yuji Harada ,  Keita Takahashi

发明人： Yoshiya Moriyama ,  Yuji Harada ,  Keita Takahashi

IPC分类号： G11C5/06

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned in the same row; and a protective diode region formed in the semiconductor region to be separated from the memory cell array region. In the protective diode region, a protective diode element is constructed by making a junction between a first diffusion layer of a second conductivity type formed in the upper portion of the semiconductor region and the semiconductor region. Each of the word lines extends to the protective diode region and is brought into direct connection to the first diffusion layer of the second conductivity type, thereby making electrical connection to the protective diode element.

摘要翻译： 半导体存储器件包括：存储单元阵列区域，形成在第一导电类型的半导体区域中，并具有以行和列排列的多个存储单元; 多个字线，其各自共同连接在同一行中排列的多个存储单元中的一个; 以及形成在半导体区域中以与存储单元阵列区域分离的保护二极管区域。 在保护二极管区域中，通过在半导体区域的上部形成的第二导电类型的第一扩散层与半导体区域之间形成接合来构成保护二极管元件。 每条字线延伸到保护二极管区，并与第二导电类型的第一扩散层直接连接，从而与保护二极管元件电连接。

公开(公告)号：US20090114998A1

公开(公告)日：2009-05-07

申请号：US12261431

申请日：2008-10-30

申请人： Yoshiya MORIYAMA

发明人： Yoshiya MORIYAMA

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/82345 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/518

摘要： A first MIS transistor is formed in a low voltage transistor formation region and includes a gate insulating film and a first gate electrode composed of a metal film and a polycrystalline silicon film. A second MIS transistor is formed in a high voltage transistor formation region and includes a gate insulating film and a second gate electrode composed of a polycrystalline silicon film. An equivalent oxide thickness of the gate insulating film formed in the low voltage transistor formation region is thinner than an equivalent oxide thickness of the gate insulating film formed in the high voltage transistor formation region. A level of the surface of a semiconductor substrate in the low voltage transistor formation region is higher than a level of the surface of a semiconductor substrate in the high voltage transistor formation region.

摘要翻译： 第一MIS晶体管形成在低压晶体管形成区域中，并且包括栅绝缘膜和由金属膜​​和多晶硅膜构成的第一栅电极。 第二MIS晶体管形成在高电压晶体管形成区域中，并且包括栅极绝缘膜和由多晶硅膜构成的第二栅电极。 形成在低压晶体管形成区域中的栅极绝缘膜的等效氧化物厚度比形成在高压晶体管形成区域中的栅极绝缘膜的等效氧化物厚度薄。 低压晶体管形成区域中的半导体衬底的表面的电平高于高压晶体管形成区域中的半导体衬底的表面的电平。

公开(公告)号：US07439577B2

公开(公告)日：2008-10-21

申请号：US11495780

申请日：2006-07-31

申请人： Takahiko Hashidzume ,  Nobuyoshi Takahashi ,  Koji Yoshida ,  Keita Takahashi ,  Kiyoshi Kurihara ,  Yoshiya Moriyama

发明人： Takahiko Hashidzume ,  Nobuyoshi Takahashi ,  Koji Yoshida ,  Keita Takahashi ,  Kiyoshi Kurihara ,  Yoshiya Moriyama

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.

摘要翻译： 半导体存储器设置有存储单元，存储单元包括由在半导体衬底中形成的扩散层构成的位线，形成在位线和形成在栅极绝缘膜上的字线之间的电荷俘获栅极绝缘膜。 在存储单元之上形成层间绝缘膜，并且在层间绝缘膜中形成位线接触插塞以连接到位线。 此外，在覆盖存储单元的层间绝缘膜的至少一部分上形成遮光膜，并且形成在层间绝缘膜上的遮光膜的一部分从层间绝缘膜的表面延伸到附近的层间绝缘膜的内部 位线接触插头。

公开(公告)号：US20070152265A1

公开(公告)日：2007-07-05

申请号：US11637939

申请日：2006-12-13

申请人： Yoshiya Moriyama ,  Yuji Harada ,  Keita Takahashi

发明人： Yoshiya Moriyama ,  Yuji Harada ,  Keita Takahashi

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned in the same row; and a protective diode region formed in the semiconductor region to be separated from the memory cell array region. In the protective diode region, a protective diode element is constructed by making a junction between a first diffusion layer of a second conductivity type formed in the upper portion of the semiconductor region and the semiconductor region. Each of the word lines extends to the protective diode region and is brought into direct connection to the first diffusion layer of the second conductivity type, thereby making electrical connection to the protective diode element.

摘要翻译： 半导体存储器件包括：存储单元阵列区域，形成在第一导电类型的半导体区域中，并具有以行和列排列的多个存储单元; 多个字线，其各自共同连接在同一行中排列的多个存储单元中的一个; 以及形成在半导体区域中以与存储单元阵列区域分离的保护二极管区域。 在保护二极管区域中，通过在半导体区域的上部形成的第二导电类型的第一扩散层与半导体区域之间形成接合来构成保护二极管元件。 每条字线延伸到保护二极管区，并与第二导电类型的第一扩散层直接连接，从而与保护二极管元件电连接。

公开(公告)号：US20070108509A1

公开(公告)日：2007-05-17

申请号：US11495780

申请日：2006-07-31

申请人： Takahiko Hashidzume ,  Nobuyoshi Takahashi ,  Koji Yoshida ,  Keita Takahashi ,  Kiyoshi Kurihara ,  Yoshiya Moriyama

发明人： Takahiko Hashidzume ,  Nobuyoshi Takahashi ,  Koji Yoshida ,  Keita Takahashi ,  Kiyoshi Kurihara ,  Yoshiya Moriyama

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.

摘要翻译： 半导体存储器设置有存储单元，存储单元包括由在半导体衬底中形成的扩散层构成的位线，形成在位线和形成在栅极绝缘膜上的字线之间的电荷俘获栅极绝缘膜。 在存储单元之上形成层间绝缘膜，并且在层间绝缘膜中形成位线接触插塞以连接到位线。 此外，在覆盖存储单元的层间绝缘膜的至少一部分上形成遮光膜，并且形成在层间绝缘膜上的遮光膜的一部分从层间绝缘膜的表面延伸到附近的层间绝缘膜的内部 位线接触插头。

公开(公告)号：US08779524B2

公开(公告)日：2014-07-15

申请号：US13554386

申请日：2012-07-20

申请人： Yoshiya Moriyama ,  Hiromasa Fujimoto ,  Satoru Itou ,  Susumu Akamatsu ,  Hiroshi Ohkawa

发明人： Yoshiya Moriyama ,  Hiromasa Fujimoto ,  Satoru Itou ,  Susumu Akamatsu ,  Hiroshi Ohkawa

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L29/7843 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L23/485 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1

摘要翻译： 半导体器件包括第一导电型第一MIS晶体管和第二导电型第二MIS晶体管。 第一和第二MIS晶体管包括形成在由半导体衬底的分离区围绕的第一和第二有源区上的第一和第二栅极绝缘膜，以及形成在第一和第二栅极绝缘上的第一和第二栅电极 电影。 第一和第二栅极绝缘膜在分离区域的第一分离区域上彼此分离。 在第一和第二有源区域的第一端之间的距离为第一和第二有源区域之间的距离，第一分隔区域彼此相对，并且从第一有源区域的第一端到第一栅极绝缘膜的第一端的突出量d1 在第一分离区域建立关系d1 <0.5s。

公开(公告)号：US20120280328A1

公开(公告)日：2012-11-08

申请号：US13554386

申请日：2012-07-20

申请人： Yoshiya MORIYAMA ,  Hiromasa FUJIMOTO ,  Satoru ITOU ,  Susumu AKAMATSU ,  Hiroshi OHKAWA

发明人： Yoshiya MORIYAMA ,  Hiromasa FUJIMOTO ,  Satoru ITOU ,  Susumu AKAMATSU ,  Hiroshi OHKAWA

IPC分类号： H01L27/092

CPC分类号： H01L29/7843 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L23/485 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1

摘要翻译： 半导体器件包括第一导电型第一MIS晶体管和第二导电型第二MIS晶体管。 第一和第二MIS晶体管包括形成在由半导体衬底的分离区围绕的第一和第二有源区上的第一和第二栅极绝缘膜，以及形成在第一和第二栅极绝缘上的第一和第二栅电极 电影。 第一和第二栅极绝缘膜在分离区域的第一分离区域上彼此分离。 在第一和第二有源区域的第一端之间的距离为第一和第二有源区域之间的距离，第一分隔区域彼此相对，并且从第一有源区域的第一端到第一栅极绝缘膜的第一端的突出量d1 在第一分离区域建立关系d1 <0.5s。