公开(公告)号：US20110073954A1

公开(公告)日：2011-03-31

申请号：US12961168

申请日：2010-12-06

申请人： Susumu AKAMATSU ,  Masafumi Tsutsui ,  Yoshinori Takami

发明人： Susumu AKAMATSU ,  Masafumi Tsutsui ,  Yoshinori Takami

IPC分类号： H01L27/092

CPC分类号： H01L21/823462 ,  H01L21/823493 ,  H01L27/11

摘要： In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

摘要翻译： 在第一部分的半导体衬底中，形成在半导体衬底的内部具有杂质浓度峰值的沟道区，在第二部分和第三部分的半导体衬底中，在 形成靠近基板表面的位置。 然后，在第一部分，第二部分和第三部分中形成延伸区域。 之后，对基板进行热处理以消除延伸区域中产生的缺陷。 然后，使用栅电极和侧壁间隔物作为掩模，在第一部分，第二部分和第三部分中形成源极/漏极区域。

公开(公告)号：US07737510B2

公开(公告)日：2010-06-15

申请号：US11545427

申请日：2006-10-11

申请人： Susumu Akamatsu

发明人： Susumu Akamatsu

IPC分类号： H01L29/76

CPC分类号： H01L29/045 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A gate insulating film and a gate electrode are formed on an active region of a semiconductor substrate. A sidewall forming an L shape in cross section is formed on the sides of the gate electrode. Source/drain regions are formed in regions of the semiconductor substrate located outside an area covering the gate electrode and the sidewall. A stress-applying stress liner film is formed to cover the gate electrode and the sidewall.

摘要翻译： 在半导体衬底的有源区上形成栅极绝缘膜和栅电极。 在栅电极的侧面上形成横截面为L形的侧壁。 源极/漏极区域形成在位于覆盖栅电极和侧壁的区域外的半导体衬底的区域中。 形成应力施加应力衬垫膜以覆盖栅电极和侧壁。

公开(公告)号：US20070096183A1

公开(公告)日：2007-05-03

申请号：US11500940

申请日：2006-08-09

申请人： Hisashi Ogawa ,  Naoki Kotani ,  Susumu Akamatsu ,  Chiaki Kudo

发明人： Hisashi Ogawa ,  Naoki Kotani ,  Susumu Akamatsu ,  Chiaki Kudo

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L21/336 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/0629 ,  H01L27/0251 ,  H01L28/20

摘要： In a semiconductor device including a MIS transistor with a FUSI gate electrode and a polysilicon resistor, a portion of the polysilicon resistor provided in a contact formation region is silicided simultaneously with the gate electrode or an impurity diffusion region.

摘要翻译： 在包括具有FUSI栅电极的MIS晶体管和多晶硅电阻器的半导体器件中，设置在接触形成区域中的多晶硅电阻器的一部分与栅极电极或杂质扩散区域同时被硅化。

公开(公告)号：US06660601B2

公开(公告)日：2003-12-09

申请号：US09938527

申请日：2001-08-27

申请人： Satoe Miyata ,  Hiroyuki Umimoto ,  Michikazu Matsumoto ,  Susumu Akamatsu

发明人： Satoe Miyata ,  Hiroyuki Umimoto ,  Michikazu Matsumoto ,  Susumu Akamatsu

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/7833

摘要： Ions of boron as a dopant are implanted using a gate electrode and an isolation film as a mask, thereby forming an ion-implanted layer as a prototype for an extended heavily doped layer. In this process step, a peak concentration of the dopant existing in the ion-implanted layer is set close to, and equal to or less than, a solid solubility at a process temperature for a first annealing process. Then, almost all of the dopant existing in the extended heavily doped layer is activated by performing the first annealing process. Thereafter, a sidewall and an ion-implanted layer as a prototype for a heavily doped source/drain layer are formed, and then the heavily doped source/drain layer is defined by performing a second RTA process.

公开(公告)号：US5396096A

公开(公告)日：1995-03-07

申请号：US132323

申请日：1993-10-06

申请人： Susumu Akamatsu ,  Atsuhiro Kajiya

发明人： Susumu Akamatsu ,  Atsuhiro Kajiya

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L21/823807 ,  H01L21/76218 ,  H01L27/0928

摘要： In a semiconductor device, a FET and an isolation are provided on a semiconductor substrate and a channel stop region is provided under the isolation. At least a region to which a high voltage is applied of a source region and a drain region of the FET is separated from the channel stop region, and a first buffer region doped with an impurity for adjusting the threshold level is provided therebetween. A region under a gate electrode and adjacent to the isolation serves as a second buffer region to which an impurity for adjusting the threshold level is doped. With the first buffer region, a depletion region at a boundary of the drain region and the channel stop region is ensured, obtaining a superior durability to high voltage of the source/drain region. With the second buffer region, leakage current between the source region and the drain region is prevented.

摘要翻译： 在半导体装置中，在半导体基板上设置FET和隔离，在隔离下设置沟道停止区域。 至少一个施加FET的源极区域和漏极区域的高电压的区域与沟道停止区域分离，并且在其间提供掺杂有用于调节阈值电平的杂质的第一缓冲区域。 在栅电极下方并且与隔离相邻的区域用作掺杂用于调整阈值电平的杂质的第二缓冲区域。 利用第一缓冲区域，确保漏极区域和沟道停止区域的边界处的耗尽区域，从而获得对源极/漏极区域的高电压的优异的耐久性。 利用第二缓冲区域，防止源极区域和漏极区域之间的漏电流。

公开(公告)号：US20120146154A1

公开(公告)日：2012-06-14

申请号：US13399102

申请日：2012-02-17

申请人： SATORU ITOU ,  HIROMASA FUJIMOTO ,  SUSUMU AKAMATSU ,  TOSHIE KUTSUNAI

发明人： SATORU ITOU ,  HIROMASA FUJIMOTO ,  SUSUMU AKAMATSU ,  TOSHIE KUTSUNAI

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.

摘要翻译： 半导体器件包括第一和第二MIS晶体管。 第一和第二MIS晶体管包括形成在第一和第二有源区上的第一和第二栅电极，其间形成有第一和第二栅极绝缘膜，第一和第二侧壁包括形成在第一和第二内侧壁上的第一和第二内侧壁 所述第一和第二栅电极的侧表面具有L形横截面，以及在所述第一和第二有源区中形成在所述第一和第二侧壁的横向外侧的第一和第二源/漏区。 第一源极/漏极区域包括形成在设置在第一有源区域中的沟槽中的硅化合物层，并且在第一有源区域中的沟道区域的栅极长度方向上产生第一应力。 第一内侧壁的宽度小于第二内侧壁的宽度。

公开(公告)号：US20080036014A1

公开(公告)日：2008-02-14

申请号：US11806882

申请日：2007-06-05

申请人： Susumu Akamatsu ,  Masafumi Tsutsui ,  Yoshinori Takami

发明人： Susumu Akamatsu ,  Masafumi Tsutsui ,  Yoshinori Takami

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L21/823462 ,  H01L21/823493 ,  H01L27/11

摘要： In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.

摘要翻译： 在第一部分的半导体衬底中，形成在半导体衬底的内部具有杂质浓度峰值的沟道区，在第二部分和第三部分的半导体衬底中，在 形成靠近基板表面的位置。 然后，在第一部分，第二部分和第三部分中形成延伸区域。 之后，对基板进行热处理以消除延伸区域中产生的缺陷。 然后，使用栅电极和侧壁间隔物作为掩模，在第一部分，第二部分和第三部分中形成源极/漏极区域。

公开(公告)号：US07288807B1

公开(公告)日：2007-10-30

申请号：US11518168

申请日：2006-09-11

申请人： Susumu Akamatsu

发明人： Susumu Akamatsu

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/66545

摘要： After a capacitor forming portion is formed on a semiconductor substrate by patterning an insulating film and a silicon film, a sidewall insulating film is formed on each of the side surfaces of the capacitor forming portion. Then, the insulating film is selectively removed such that the silicon film is exposed in a depressed portion surrounded by the sidewall insulating film. Subsequently, a first metal film is deposited and then a thermal process is performed to change the silicon film into a first metal film. Thereafter, an insulating film and a second metal film are buried in the depressed portion. The insulating film composes the capacitor insulating film of a capacitor element. The first metal silicide film and the second metal film compose the lower and upper electrodes of the capacitor element, respectively.

摘要翻译： 在通过图案化绝缘膜和硅膜在半导体衬底上形成电容器形成部分之后，在电容器形成部分的每个侧表面上形成侧壁绝缘膜。 然后，选择性地去除绝缘膜，使得硅膜暴露在由侧壁绝缘膜包围的凹陷部分中。 随后，沉积第一金属膜，然后进行热处理以将硅膜改变为第一金属膜。 此后，绝缘膜和第二金属膜被埋在凹陷部分中。 绝缘膜构成电容器元件的电容绝缘膜。 第一金属硅化物膜和第二金属膜分别构成电容器元件的下电极和上电极。

公开(公告)号：US20070173025A1

公开(公告)日：2007-07-26

申请号：US11540762

申请日：2006-10-02

申请人： Susumu Akamatsu

发明人： Susumu Akamatsu

IPC分类号： H01L21/336

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： First and second gate portions each made of a gate insulating film, a silicon film, and a protective film are formed on a semiconductor substrate. Then, a first sidewall insulating film is formed on each of the side surfaces of the first and second gate portions. Subsequently, the protective film is removed such that the silicon film is exposed. A thermal process is performed with respect to a Ni film deposited on the silicon film to convert the silicon film to a NiSi film and then an insulating film is formed on the NiSi film. Thereafter, a Ni film is deposited on the NiSi film and a thermal process is performed to convert the NiSi film to a Ni3Si film.

摘要翻译： 在半导体基板上形成由栅极绝缘膜，硅膜和保护膜构成的第一和第二栅极部。 然后，在第一和第二栅极部分的每个侧表面上形成第一侧壁绝缘膜。 随后，去除保护膜，使得硅膜暴露。 对沉积在硅膜上的Ni膜进行热处理，将硅膜转化为NiSi膜，然后在NiSi膜上形成绝缘膜。 此后，在NiSi膜上沉积Ni膜，并进行热处理以将NiSi膜转变成Ni 3 Si膜。

公开(公告)号：US20070158721A1

公开(公告)日：2007-07-12

申请号：US11545521

申请日：2006-10-11

申请人： Susumu Akamatsu

发明人： Susumu Akamatsu

IPC分类号： H01L29/94

CPC分类号： H01L21/823878 ,  H01L21/76229 ,  H01L21/823807

摘要： A trench isolation surrounding the lateral sides of an active region of a P-channel MIS transistor PTr and a trench isolation surrounding the lateral sides of an active region of an N-channel MIS transistor NTr have different film qualities.

摘要翻译： 围绕P沟道MIS晶体管PTr的有源区域的侧面的沟槽隔离以及围绕N沟道MIS晶体管NTr的有源区域的横向侧面的沟槽隔离具有不同的膜质量。