公开(公告)号：US07809339B1

公开(公告)日：2010-10-05

申请号：US11715027

申请日：2007-03-07

申请人： Swee-Ann Teo ,  Lawrence Tse ,  Yonghua Song

发明人： Swee-Ann Teo ,  Lawrence Tse ,  Yonghua Song

IPC分类号： H04B1/04 ,  H04B7/00

CPC分类号： H04B1/40 ,  H03G3/004

摘要： A voltage regulator comprises a master regulator circuit that receives a reference signal and that generates a feedback signal and a master bias signal. The master bias signal is based on the reference signal and the feedback signal. N slave regulator circuits receive the master bias signal from the master regulator circuit and output N regulated output signals to N circuits, respectively, where N is an integer greater than one.

摘要翻译： 电压调节器包括接收参考信号并产生反馈信号和主偏置信号的主调节器电路。 主偏置信号基于参考信号和反馈信号。 N个从调节器电路从主调节器电路接收主偏置信号，并分别将N个调节输出信号输出到N个电路，其中N是大于1的整数。

公开(公告)号：US07190936B1

公开(公告)日：2007-03-13

申请号：US10747522

申请日：2003-12-29

申请人： Swee-Ann Teo ,  Lawrence Tse ,  Yonghua Song

发明人： Swee-Ann Teo ,  Lawrence Tse ,  Yonghua Song

IPC分类号： H04B1/04 ,  H04B1/06

CPC分类号： H04B1/40 ,  H03G3/004

摘要： A voltage regulator includes a master regulator circuit that receives a reference signal, that generates a master bias signal and that includes a transistor having a first gain. A first slave regulator circuit includes a first transistor having a second gain that is substantially equal to unity gain, a control terminal that receives the master bias signal from the master regulator circuit, a first terminal and a second terminal that outputs a first regulated output signal. A second slave regulator circuit includes a second transistor having a second gain that is substantially equal to unity gain, a control terminal that receives the master bias signal from the master regulator circuit, a first terminal, and a second terminal that outputs a second regulated output signal.

摘要翻译： 电压调节器包括主调节器电路，其接收产生主偏置信号并且包括具有第一增益的晶体管的参考信号。 第一从调节器电路包括具有基本上等于单位增益的第二增益的第一晶体管，从主调节器电路接收主偏置信号的控制端，输出第一调节输出信号的第一端和第二端， 。 第二从调节器电路包括具有基本上等于单位增益的第二增益的第二晶体管，从主调节器电路接收主偏置信号的控制端，第一端和输出第二调节输出的第二端 信号。

公开(公告)号：US08331884B1

公开(公告)日：2012-12-11

申请号：US12893604

申请日：2010-09-29

申请人： Swee-Ann Teo ,  Lawrence Tse ,  Yonghua Song

发明人： Swee-Ann Teo ,  Lawrence Tse ,  Yonghua Song

IPC分类号： H04B1/04 ,  H04B1/06

CPC分类号： H04B1/40 ,  H03G3/004

摘要： A voltage regulator for a radio frequency circuit including a master regulator circuit, a first slave regulator circuit, and a first radio frequency subcircuit. The master regulator circuit is configured to i) receive a reference voltage signal and a feedback signal and ii) output a control voltage signal based on the reference voltage signal and the feedback signal. The first slave regulator circuit is configured to i) receive the control voltage signal and ii) output a first regulated supply voltage signal based on the control voltage signal. The first radio frequency subcircuit is configured to receive the first regulated supply voltage signal. The control voltage signal corresponds to a desired supply voltage for the first radio frequency subcircuit.

摘要翻译： 一种用于射频电路的电压调节器，包括主调节器电路，第一从调节器电路和第一射频子电路。 主调节器电路被配置为i）接收参考电压信号和反馈信号，以及ii）基于参考电压信号和反馈信号输出控制电压信号。 第一从调节器电路被配置为i）接收控制电压信号，以及ii）基于控制电压信号输出第一稳压电源电压信号。 第一射频分支电路被配置为接收第一稳压电源电压信号。 控制电压信号对应于第一射频子电路的期望电源电压。

公开(公告)号：US07899422B1

公开(公告)日：2011-03-01

申请号：US11626829

申请日：2007-01-24

申请人： Swee-Ann Teo ,  Yonghua Song

发明人： Swee-Ann Teo ,  Yonghua Song

IPC分类号： H04B1/40

CPC分类号： H03L7/1976 ,  H03L7/081 ,  H03L7/0998

摘要： A sigma delta modulated phase lock loop reduces quantization noise by using phase interpolation to increase an effective frequency resolution of the dividing ratio of a divider.

摘要翻译： Σ-Δ调制锁相环通过使用相位插值来减小量化噪声，以增加分频器的分频比的有效频率分辨率。

公开(公告)号：US07181180B1

公开(公告)日：2007-02-20

申请号：US10738368

申请日：2003-12-15

申请人： Swee-Ann Teo ,  Yonghua Song

发明人： Swee-Ann Teo ,  Yonghua Song

IPC分类号： H04B1/40 ,  H03L7/197

CPC分类号： H03L7/1976 ,  H03L7/081 ,  H03L7/0998

摘要： A sigma delta modulated phase lock loop reduces quantization noise by using phase interpolation to increase an effective frequency resolution of the dividing ratio of a divider.

摘要翻译： Σ-Δ调制锁相环通过使用相位插值来减小量化噪声，以增加分频器的分频比的有效频率分辨率。

公开(公告)号：US07454634B1

公开(公告)日：2008-11-18

申请号：US11070481

申请日：2005-03-02

申请人： Timothy Donovan ,  Shafiq Jamal ,  Yonghua Song ,  Chia-Chun Chung ,  Tam Tran ,  Lawrence Tse

发明人： Timothy Donovan ,  Shafiq Jamal ,  Yonghua Song ,  Chia-Chun Chung ,  Tam Tran ,  Lawrence Tse

IPC分类号： G06F1/32

CPC分类号： H04W52/029 ,  Y02D70/142 ,  Y02D70/22

摘要： A wireless network device having active and inactive modes comprises a clock generating module that generates a first clock signal having a first clock rate. A voltage supply module generates a first voltage level and a second voltage level that is less than the first voltage level. A first digital module receives the first clock rate and the first voltage level during the active mode, receives the second voltage level during the inactive mode and does not receive the first clock signal during the inactive mode. A first analog module communicates with the voltage supply module and has reduced current consumption during the inactive mode.

摘要翻译： 具有有源和不活动模式的无线网络设备包括产生具有第一时钟速率的第一时钟信号的时钟产生模块。 电压供应模块产生小于第一电压电平的第一电压电平和第二电压电平。 第一数字模块在活动模式期间接收第一时钟速率和第一电压电平，在非活动模式期间接收第二电压电平，并且在非活动模式期间不接收第一时钟信号。 第一模拟模块与电压供应模块通信，并且在非活动模式期间具有减少的电流消耗。

公开(公告)号：US09184839B1

公开(公告)日：2015-11-10

申请号：US13566157

申请日：2012-08-03

申请人： Songping Wu ,  Daxiao Yu ,  Yonghua Song

发明人： Songping Wu ,  Daxiao Yu ,  Yonghua Song

IPC分类号： H04B10/2507 ,  H04B17/20

CPC分类号： H04B17/17

摘要： The present disclosure describes techniques for identity-based RF circuitry compensation. In some aspects data from a wireless device is received via radio frequency circuitry, the data including an identifier that uniquely identifies the wireless device. Impairments of the radio frequency circuitry are estimated based on the received data and then the estimated impairments are associated with the identifier of the wireless device. In response to subsequently receiving data that includes the identifier, the radio frequency circuitry is compensated using the estimated impairments.

摘要翻译： 本公开描述了用于基于身份的RF电路补偿的技术。 在一些方面，来自无线设备的数据经由射频电路接收，该数据包括唯一地标识无线设备的标识符。 基于接收到的数据来估计射频电路的损害，然后估计的损伤与无线设备的标识符相关联。 响应于随后接收包括标识符的数据，使用估计的损伤来补偿射频电路。

公开(公告)号：US07664204B1

公开(公告)日：2010-02-16

申请号：US11078717

申请日：2005-03-10

申请人： Hui Wang ,  Yonghua Song

发明人： Hui Wang ,  Yonghua Song

IPC分类号： H04L27/00 ,  H03D3/24

CPC分类号： H04L27/0014 ,  H04L2027/0036 ,  H04L2027/0053 ,  H04L2027/0065 ,  H04L2027/0067 ,  H04L2027/0091

摘要： Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.

摘要翻译： 提供电路和方法，用于在近似主机时钟信号的频率时调整本地时钟信号的频率。 锁相环产生具有第一相位和第一频率的本地时钟信号。 偏移调整电路接收与输入数据信号相关的本地时钟信号的定时信息，并计算出相应的偏移和指示对本地时钟信号进行调整的频率偏移。 第一相位内插器从本地时钟信号产生接收时钟信号，接收时钟信号具有响应于相位和频率偏移的第二相位和第二频率。 第二相位插值器响应于频率偏移从具有第三频率的本地时钟信号产生发送时钟信号。

公开(公告)号：US07528657B1

公开(公告)日：2009-05-05

申请号：US11699890

申请日：2007-01-30

申请人： Donghong Cui ,  Yonghua Song

发明人： Donghong Cui ,  Yonghua Song

IPC分类号： H03F3/45

CPC分类号： H03F3/45094 ,  H03F1/34 ,  H03F3/45475 ,  H03F3/72 ,  H03F2203/45521

摘要： An electrical circuit comprises a plurality of amplifiers. Each of the plurality of amplifiers comprises an input circuit in communication with an input of the amplifier and a start-up circuit in communication with the input circuit. The start-up circuit is configured to generate a start-up signal to enable subsequent operation of the amplifier. An output circuit communicates with an output of the amplifier and with the input circuit and the start-up circuit. Respective inputs of a first and a second amplifier of the plurality of amplifiers are in communication with outputs of a third amplifier of the plurality of amplifiers. Outputs of the second amplifier are in communication with inputs of the third amplifier.

摘要翻译： 电路包括多个放大器。 多个放大器中的每一个包括与放大器的输入通信的输入电路和与输入电路通信的启动电路。 启动电路被配置为产生启动信号以使能放大器的后续操作。 输出电路与放大器的输出以及输入电路和启动电路进行通信。 多个放大器的第一和第二放大器的相应输入端与多个放大器的第三放大器的输出端相通。 第二放大器的输出与第三放大器的输入端通信。

公开(公告)号：US07259600B1

公开(公告)日：2007-08-21

申请号：US11542978

申请日：2006-10-04

申请人： Yonghua Song

发明人： Yonghua Song

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/0805

摘要： An integrated circuit architecture comprises a phase lock loop (PLL) circuit that includes a feedback circuit that receives a reference signal. A voltage controlled oscillator (VCO) generates an output signal to an input of the feedback circuit. A master transistor has a control terminal, a first terminal, and a second terminal that communicates with the VCO. The feedback circuit compares the output signal of the VCO to the reference signal and outputs a drive signal to the control terminal of the master transistor based on the comparison. N slave transistors have control terminals that communicate with the control terminal of the master transistor, first terminals, and second terminals.

摘要翻译： 集成电路架构包括锁相环（PLL）电路，其包括接收参考信号的反馈电路。 压控振荡器（VCO）产生到反馈电路的输入端的输出信号。 主晶体管具有与VCO通信的控制端子，第一端子和第二端子。 反馈电路将VCO的输出信号与参考信号进行比较，并根据比较将驱动信号输出到主晶体管的控制端。 N个从属晶体管具有与主晶体管，第一端子和第二端子的控制端子通信的控制端子。